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Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

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Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

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Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

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ELEC 5970-003/6970-003 (Fall 2004)Advanced Topics in Electrical EngineeringDesigning VLSI for Low-Power and Self-TestEstimating Power Consumption

Vishwani D. Agrawal

James J. Danaher Professor

Department of Electrical and Computer Engineering

Auburn University

http://www.eng.auburn.edu/~vagrawal

vagrawal@eng.auburn.edu

ELEC 5970-003/6970-003

- Logic simulation
- Circuit-level simulation
- Probabilistic estimation
- Peak power estimation
- Power estimation for a high-level design

ELEC 5970-003/6970-003

Ca

VDD

pMOS FETs

a

Da

c

Dc

a

b

Db

c

Cc

b

Daand Dbare

interconnect or

propagation delays

Dcis inertial delay

of gate

Cb

nMOS FETs

Ca , Cb and Cc are

parasitic capacitances

ELEC 5970-003/6970-003

Transient

region

a

Inputs

b

c (CMOS)

c (zero delay)

c (unit delay)

Logic simulation

X

rise=5, fall=5

c (multiple delay)

Unknown (X)

c (minmax delay)

min =2, max =5

Time units

5

0

ELEC 5970-003/6970-003

- Two-states (0, 1) can be used for purely combinational logic with zero-delay.
- Three-states (0, 1, X) are essential for timing hazards and for sequential logic initialization.
- Four-states (0, 1, X, Z) are essential for MOS devices. See example below.
- Analog signals are used for exact timing of digital logic and for analog circuits.

Z

(hold previous value)

0

0

ELEC 5970-003/6970-003

- Event-driven simulation
- Only gates or modules with input events are evaluated (event means a signal change)
- Gate and interconnect delays are used to determine the transients at gate outputs
- Per-vector complexity of computation is linear in number of gates × total input to output time delay units

ELEC 5970-003/6970-003

Scheduled

events

c = 0

d = 1, e = 0

g = 0

f = 1

g = 1

Activity

list

d, e

f, g

g

a =1

e =1

t = 0

1

2

3

4

5

6

7

8

2

c =1→0

g =1

2

2

d = 0

4

f =0

b =1

Time stack

g

8

4

0

Time, t

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max

Current

time

pointer

t=0

Event link-list

1

2

3

4

5

6

7

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- For every vector (changes at primary input):
- At every signal node (gate output):
- Count number of transitions
- Compute #transitions × node capacitance × VDD2/2
- If node capacitances are not known, use fanout approximation – often used for relative power comparison between circuits
- Add pre-estimated leakage power for vector period

- At every signal node (gate output):

ELEC 5970-003/6970-003

- Event-driven simulator
- Switch-level simulation with delays
- 2-3 orders of magnitude faster than Spice
- Estimates power for given vectors, due to
- Instantaneous, average and rms currents
- Steady-state transitions and glitches
- Short-circuit and leakage currents

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- Determines current density and voltage drop in the power net
- Points to potential problem areas on a VLSI chip for EM failures, ground bounce, excessive voltage drop, heating
- Reference: C. Deng, “Power Analysis for CMOS/BiCMOS Circuits,” Proc. International Workshop on Low Power Design, April 1994, pp. 3-8.

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1

Channel-connected components

1

0

?

1

1

R. E. Bryant, “A Survey of Switch-Level

Algorithms,” IEEE Design & Test of

Computers, vol. 4, no. 4, pp. 26-40,

August 1987.

1

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- Gate-level circuit is partitioned into cells.
- Cells are simulated in Spice for power dissipation for all possible input events.
- Logic simulation determines the events at cell inputs, adding the corresponding power dissipated by each cell.
- B. J. George, D. Gossain, S. C. Tyler, M. G. Wloka, and G. K. H. Yeap, “Power Analysis and Characterization for Semi-Custom Design,” Proc. International Workshop on Low Power Design, April 1994, pp. 215-218.

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- Two step procedure:
- Behavioral simulation to collect the input statistics for all modules in RTL description
- Develop power macro-model for each module and sum the power

- Q. Wu, C.-S. Ding, C.-T. Hsieh, and M. Pedram, “Statistical Design of Macro-Models for RT-Level Power Estimation,” Proc. Second Asia-Pacific Design Automation Conference, Jan. 1997.

ELEC 5970-003/6970-003

- Module description is modified to collect input statistics.
- Example: 16-bit multiplier module

c = a*b;

r1 = a^a’;

r2 = b^b’;

for (i=0; i <16; i++ ) {

sw_a[ i ] += r1 & 1;

sw_b[ i ] += r2 & 1;

r1 = r1 >> 1;

r2 = r2 >> 1;

}

a’ = a;

b’ = b;

ELEC 5970-003/6970-003

- Develop analytic models for estimating the switched capacitance as a function of circuit complexity and technology/library parameters. OR
- Synthesize the circuit and then estimate power dissipation by simulation with random vectors.
- Both methods determine effective switched capacitance per input transition.

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Power dissipation of a module = 0.5 V2f C E

- where
- V is supply voltage
- f is vector frequency
- C is effective switched capacitance/input transition
- E is input activity (bit changes) per vector

ELEC 5970-003/6970-003

- Signal probability: Expected value of a binary signal, s

T

E(s)= lim (1/T)∫ s(t) dt = Prob(s=1) = p(s)

=1.p(s) + 0.(1-p(s))

t=0

ELEC 5970-003/6970-003

psw(s(t))= p(s(t-ε))(1-p(s(t))) + (1-p(s(t-ε)))p(s(t))

=p(s(t-ε)) + p(s(t)) – 2p(s(t-ε))p(s(t))

If p(s(t-ε)) = p(s(t)) = p(s), then

psw(s(t))=2p(s)(1-p(s))

Dynamic power= 0.5 CVDD2psw(s(t)) f

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- NOT: c = a, p(c) = 1 – p(a)
- AND: c = ab,p(c) = p(a)p(b)
- OR: c = a+b, p(c) = 1 - (1-p(a))(1-p(b))
= p(a) + p(b) – p(a)p(b)

ELEC 5970-003/6970-003

p(a) = 0.5

0.25

p(c) = 0.5

0.25+0.25-0.0625

= 0.4375

output

0.5

Switching probability

psw(output)

= 2×0.4375×(1-0.4375)

= 0.4921875

0.25

p(b) = 0.5

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p(output) = 0.5 psw(output) = 2×0.5×0.5 = 0.5

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p(a) = 0.5

p(a)p(c) = 0.25

0.25+0.25-0.0625

= 0.4375

p(c) = 0.5

output

1-p(c) = 0.5

p(a)p(c) + p(b)(1-p(c))

- p(a)p(b)p(c)(1-p(c))

=p(a)p(c)+p(b)-p(b)p(c)

= 0.5

p(b)(1-p(c)) = 0.25

p(b) = 0.5

K. P. Parker and E. J. McCluskey, Probabilistic Treatment of General

Combinational Networks,” IEEE Trans. Computers, vol. C-24, no. 6,

pp. 668-670, June 1975.

ELEC 5970-003/6970-003

a

c

output

b

Supergate of a signal is the smallest circuit partition including all

fanout stems dominated by that signal.

Supergate(output)

S. C. Seth and V. D. Agrawal, “A New Method for Computation of

Probabilistic Testability in Combinational Circuits,” Integration, the VLSI

Journal, vol. 7, no. 1, pp. 49-75, April 1989.

ELEC 5970-003/6970-003

- To calculate p(output), enumerate signal states at fanout signal(s) – c in this example.
- For each case i, compute pi(output) separately.
- Compute
p(output) = p(c)p1(output) + (1-p(c))p0(output)

ELEC 5970-003/6970-003

p(a)=0.5

p(a)=0.5

0.5

0.0

0.5

c=1

0.5

c=0

0

1

output

output

0.0

0.5

p (b)=0.5

p (b)=0.5

P(output) = p(c) 0.5 + (1-p(c)) 0.5 = 0.5

ELEC 5970-003/6970-003

- Weighted averaging
- B. Krishnamurthy and I. G. Tollis, “Improved Techniques for Estimating Signal Probabilities,” IEEE Trans. Computers, vol. C-38, no. 7, pp. 1245-1251, July 1989.

- Cutting algorithm
- J. Savir, G. Ditlow and P. Bardell, “Random Pattern Testability,” IEEE Trans. Computers, vol. C-33, no. 1, pp. 79-90, Jan. 1989.

- OBDD
- R. E. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation,” IEEE Trans. Computers, vol. C-35, no. 8, pp. 677-691, Aug. 1989.

- Transition density
- F. N. Najm, “Transition Density: A New Measure of Activity in Digital Circuits,” IEEE Trans. CAD, vol. 12, no. 2, pp. 310-323, Feb. 1993.

ELEC 5970-003/6970-003

- Signal probability methods do not take delays into account. Hence, glitch power is not included.
- Timed symbolic simulation
- A Ghosh, S. Devadas, K. Keutzer and J. White, “Estimation of Average Switching Activity in Combinational and Sequential Circuits,” Proc. 29th Design Automation Conf., June 1992, pp. 253-259.

- Probability waveform simulation
- C.-S. Ding, C.-Y. Tsui and M. Pedram, “Gate-Level Power Estimation Using Tagged Probabilistic Simulation,” IEEE Trans. CAD, vol. 17, no. 11, pp. 1099-1107, Nov. 1998.

ELEC 5970-003/6970-003