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Combinational Logic. Chapter 4. Combinational Circuits. Combinational Circuits. Adders Subtractors Comparators Decoders Encoders Multiplexers

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combinational circuits1
Combinational Circuits
  • Adders
  • Subtractors
  • Comparators
  • Decoders
  • Encoders
  • Multiplexers

Available as MSI Circuits and as Standard Cells in VLSI (Bonus Assignment: Get one example of each type of combinational circuits in the CMOS family, 5 points for the second exam)

analysis procedure
Analysis Procedure
  • Given a logical diagram, determine one or more of the following:
    • Boolean functions;
    • Truth table;
    • Explanation of circuit operation
  • Make sure the circuit is combinational, not sequential (No feedback loops)
analysis procedure1
Analysis Procedure
  • Label all gate outputs that are a function of input variables. Determine the Boolean function for each gate output
  • Label the gates that are a function of input variables and previously labeled gates. Find the Boolean functions for these gates
  • Repeat step 2 until output of circuits are obtained
  • By repeated substitution of previously defined functions, obtain the output Boolean functions in terms of input variables
analysis procedure3
Analysis Procedure

Step 1

Step 2

Steps 3 and 4

analysis procedure4
Analysis Procedure
  • Determine the number of input variables in the circuit. For inputs, form the possible input combinations and list the binary numbers from to in a table
  • Label the outputs of selected gates with arbitrary symbols
  • Obtain the truth table for the outputs of those gates which are a function of the input variables only
  • Proceed to obtain the truth table for the outputs of those gates which are a function of previously defined values until the columns for all outputs are determined
design procedure
Design Procedure
  • From the specifications of the circuit, determine the required number of inputs and outputs and assign a symbol to each
  • Derive the truth table that defines the required relationship between inputs and outputs
  • Obtain the simplified Boolean functions for each output as a function of the input variables
  • Draw the logical diagram and verify correctness of the design
full adder1
Full adder

Implementation of full adder in sum-of-products

full adder3
Full adder

Implementation of full adder using two half adders and one or gate

carry propagation
Carry propagation

Carry Generate

Full Adder with and shown

carry propagation1
Carry propagation

Carry lookahead generator

four bit adder with carry lookahead
Four-bit adder with carry lookahead

Carry lookahead generator

  • Occurs only when adding two positive numbers or two negative numbers;
  • Overflow produces change in result sign

Example: eight-bit adder

Carry bits

decimal adder
Decimal Adder
  • Consider adding two decimal digits in BCD
  • Output sum cannot exceed 9+9+1=19 (the last 1 is the carry from previous digit)
decimal adder1
Decimal Adder


Need correction

Condition for correcting result

binary multiplier
Binary Multiplier



Explain how you carried the multiplication out. How many bits at the output?

binary multiplier1
Binary Multiplier

Two-bit multiplier

binary multiplier2
Binary Multiplier

Exercise: With your neighbor classmate discuss its operation.

magnitude comparator
Magnitude Comparator

Exercise: Discuss with your neighbor classmate and write down how you would compare two four-bit binary numbers and , where and . You should have three outputs corresponding to , , and . Explain how you determined each condition.

magnitude comparator1
Magnitude Comparator

Does this circuit correspond to what you wrote down in the exercise? Discuss again with your neighbor classmate the comparison of your result with this circuit.


Exercise: Minimize the functions for two of the eight output lines.


Exercise: Compare your function with the circuit.

Three-to-eight-line decoder


decoder constructed with two decoders

Exercise: Explain how this decoder works.

combinational logic implementation
Combinational logic implementation

Exercise: For the maps of the full adder shown above, express the sum (left) and the carry bit (right) as a sum of minterms.

combinational logic implementation1
Combinational Logic Implementation

Compare in terms of propagation time and number of gates this Full Adder with the previously studied implementation.

priority encoder
Priority encoder

Highest priority

Valid output

priority encoder1
Priority encoder

Exercise: obtain the function for

  • Selects binary information from one of many input lines
  • Directs input line to output, controlled by a set of selection lines
  • input lines and selection lines

Two-to-one-line multiplexer


Four-to-one-line multiplexer


Quadruple two-to-one-line multiplexer

boolean function implementation
Boolean function implementation
  • Multiplexer is essentially a decoder with OR gates
  • Thus can implement Boolean functions, similar to decoders
  • Minterms generated by circuit associated with selection inputs
  • Individual minterms can be selected by data inputs
  • Boolean function of variables and data inputs
boolean function implementation1
Boolean function implementation
  • More efficient method for implementing a Boolean function of variables with multiplexer of selection inputs
  • Remaining variable of function is used for the data inputs
boolean function implementation2
Boolean function implementation
  • Example:

Selected input line





Implementation of a three-input Boolean function

three state gates1
Three-state gates

Multiplexers with three-state gates

homework assignment
Homework Assignment
  • 4.3
  • 4.9
  • 4.17
  • 4.27
  • 4.33
  • Using LogicWorks, simulate a 4-bit full adder with and without carry-lookahead.