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Dynamic Resistance – Key to Superior Clamping http://www.littelfuse.com/data/en/Application_Notes/Littelfuse-Selecting_an_Appropriate_ESD_Device.pdf.
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Dynamic Resistance– Key to Superior Clampinghttp://www.littelfuse.com/data/en/Application_Notes/Littelfuse-Selecting_an_Appropriate_ESD_Device.pdf • The figure below depicts an ESD protection device as a variable resistor which will be high impedance (low leakage) during normal circuit operation and low impedance during any EOS (Electrical Over Stress) or ESD event. • The ultimate goal of a protection device is to provide the lowest resistance shunt path to GND under an ESD event. • Ideally, all current would be steered into the ESD device so that the protected IC would not have to dissipate any of the energy input into the circuit. • Lower RDYN = Lower clamping voltage = Better, more robust protection *SPA’s, in general, tend to have the lowest dynamic resistance per capacitance of any of the ESD protection technologies.
Why does dynamic resistance matter in an application? CLAMPING VOLTAGE! Decreasing the clamping voltage reduces the stress on the chipset. -ESD pulse is 8kV, contact discharge, per IEC 61000-4-2 *Data of Littelfuse’s SP1003-01DTG vs. a competitor’s varistor. *Both devices have the same footprint (0402), same standoff voltage, and similar capacitances. Peak Voltage = 240V vs. 156V Clamp Voltage = 75V vs. 16V The area between the curves represents the amount of energy that DOES NOT get to the chip when this MLV was replaced by the SP1003-01DTG. The reduction in transient energy helps ensure that the chipset will survive even severe ESD events.