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PLURALITY. אימות רכיב מרובה מעבדים Validation of a Multi-Core Chip. מצגת אמצע Mid Presentation Project period : 2 semesters Starting semester: winter 2010/2011. Performed by : Malik Kittani, Ayman Mouallem Supervisor : Moshe Bensal. PLURALITY. Plurality – Reminder.

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Validation of a multi core chip

PLURALITY

אימות רכיב מרובה מעבדיםValidation of a Multi-Core Chip

מצגת אמצע Mid Presentation

Project period : 2 semesters

Starting semester: winter 2010/2011

Performed by : Malik Kittani, Ayman Mouallem

Supervisor : Moshe Bensal


Validation of a multi core chip

PLURALITY

Plurality – Reminder

This is a Blocks diagram that describes the basics of Plurality system, the system that we are going to test through this project, with all its components.


Validation of a multi core chip

PLURALITY

Reminder About PLURALITY :

  • * The cores

    • - 16-256 of 32-RISC SPARC Hyper-core processor

    • - Perform basic arithmetic operations

  • * Co-Processor

    • - One helper unit for each 4 cores

    • - Perform multiplication and division

  • * Central Synchronization Unit (CSU) - scheduler

    • Distributes the tasks between the cores with minimal overhead

  • * Shared memory system

    • -Allows any number of cores to access data and instruction memory at every clock cycles


Validation of a multi core chip

PLURALITY

Project Objectives :

  • Understand Plurality's HAL Architecture.

  • Understand Plurality’s Simulator and its capabilities.

  • Learning, designing of several testing

  • methods for single core

  • Implementing of several testing methods for single core

  • Expanding the testing to multi-core architecture .


Validation of a multi core chip

PLURALITY

PROGRESS SO FAR :

  • Learning the compiling, execution and debugging process using the simulator and the Eclipse [done] :- we managed to test the system by running few program that were previously designed by the students of the faculty such as : Hello World , FFT, etc…and we saw that the system re-acts

  • Learning and Programming in Task Oriented Programming (TOP) method[done].

  • Learning about cornerstones of chip testing field[done] :

    • Observabilityand Controllability: we have explored what features Plurality have in order to do this.

  • Building A skeleton and ideas for the tests that we are going to build until the end of the semester [done] .

  • Midterm Presentation.


Validation of a multi core chip

PLURALITY

What are we going to test at the current semester ?!

  • Current perspective :

  • This Is a new hardware. Is every component working as it should ?!

  • Are all the components connected and can pass data between them ?

  • Is all the memory space addressable ? And can be read and written ?!

  • Are all the components needed for a single core working correctly ? (program counter, register file, ALU, FPU, Memory).


Validation of a multi core chip

PLURALITY

Problems that we faced until now :

As we have mentioned before, in the Characterization Presentation, Plurality is having financial problems, therefore we couldn’t get any support of them in order to solve the problems we faced.

We tried to cope with the problems in another ways. These ways, maybe, are not the right ways that are used in the industry. But are the best ways that we could think about, considering the lack of tools that we have in hands.

In some components, such like FPU, in order to get maximal coverage fault of the components, we must know how these components are built. And since we don’t have that information, we will assume that these components are built in a standard way.


Validation of a multi core chip

PLURALITY

Problems that we faced until now :

  • Controllability – how to control data flow :

Plurality haven’t exposed or published any paper about the features of controllability that it had in it’s chip, for example; Since we don’t have a built in DFT for registers, we can’t write to a specific register using C-language, because it depends on how the compiler translate high level language to machine language.

  • Solution:

We will try to control the data through forcing values by using assembly code of the chip.


Validation of a multi core chip

PLURALITY

Problems that we faced until now :

  • Automatic Compiler Optimizations:

When compiling C-code, the compiler make some optimizations for the code.

Therefore, after compilation, the machine code that we get is different than the one we intended to get for our test.

  • Solution:

We will give a “-o1” flag in the command line of the GCC compiler. This flag prevents the compiler of making optimizations to the assembly code that we use in the tests.

Using command line (or through eclipse) we can view the Assembly code of the test, and make sure that no optimizations were made.


Validation of a multi core chip

PLURALITY

Problems that we faced until now :

  • Memory hierarchy :

When we test the memory, we shall read and write to all the physical addresses. And since we don’t know how the memory is build, and how it’s divided between the stack, data, and instruction sections, we might write data to the instructions section or stack section that stores the data of the running test. And by doing this we will destroy the test flow.

  • Solution:

We will create files of ones and zeros or sequence of zeros and ones , and read them. After that we will dump all the memory to a file.

When we view this file, we can guess what are the physical addresses of the memory that we can validate. We will check only this area of the memory.


Validation of a multi core chip

PLURALITY

Tests Block Diagram:

In this project we managed to divide the components to five categories :

Basic Test/Program Counter

ALU

FPU

Memory

Register file


Validation of a multi core chip

PLURALITY

Tests Block Diagram:

In this project we managed to divide the components to five categories :

Basic Test/Program Counter

ALU

FPU

Memory

Register file


Validation of a multi core chip

PLURALITY

Basic Test/Program Counter:

In order to validate the program counter, we choose a well know test bench that is called “Dhrystone Benchmark”.

This benchmark includes variety of tests for assignments, control statements, procedures, and function calls.

We will re-write that test bench in away that we can run it on plurality’s hardware.


Validation of a multi core chip

PLURALITY

Tests Block Diagram:

In this project we managed to divide the components to five categories :

Basic Test/Program Counter

ALU

FPU

Memory

Register file


Validation of a multi core chip

PLURALITY

Tests Block Diagram:

In this project we managed to divide the components to five categories :

Basic Test/Program Counter

ALU

FPU

Memory

Register file


Validation of a multi core chip

PLURALITY

ALU:

We will divide the ALU test to four parts :

Basic Arithmetic Operations

Shift operations

Logic Operations

Multiplier


Validation of a multi core chip

PLURALITY

ALU:

We will divide the ALU test to four parts :

Basic Arithmetic Operations

Shift operations

Logic Operations

Multiplier


Validation of a multi core chip

PLURALITY

ALU- Shifter testing:

We adopt a deterministic test strategy that tests the shifter by performing the ROR/ROL operations 2n+3 times(where n is the word length) starting from value 1.

This test code achieves 100% fault coverage.


Validation of a multi core chip

PLURALITY

ALU:

We will divide the ALU test to four parts :

Basic Arithmetic Operations

Shift operations

Logic Operations

Multiplier


Validation of a multi core chip

PLURALITY

ALU:

We will divide the ALU test to four parts :

Basic Arithmetic Operations

Shift operations

Logic Operations

Multiplier


Validation of a multi core chip

PLURALITY

ALU- logic operations:

We adopt a deterministic test strategy that tests the “logic” part of the ALU by performing the logical operations : OR, AND, XOR, XNOR,NOT and CMP.This test strategy is general enough and it can be applied to various ALU designs.

Test pattern generation is performed by putting the four possible combinations of values all 0's and all 1's.

This test code achieves the below fault coverage [3]

WORD LENGTH ARCHITECTURE FAULT COVERAG

32 bits SEP - RCA 100.0%

32 bits SEP - CLA 99.9%

32 bits COM - CLA 99.9%

where SEP=separate arithmetic logical part of the ALU,

COM=combined arithmetic/logical part of the ALU,

RCA=ripple-carry adder and CLA=carry look ahead adder.


Validation of a multi core chip

PLURALITY

ALU:

We will divide the ALU test to four parts :

Basic Arithmetic Operations

Shift operations

Logic Operations

Multiplier


Validation of a multi core chip

PLURALITY

ALU:

We will divide the ALU test to four parts :

Basic Arithmetic Operations

Shift operations

Logic Operations

Multiplier


Validation of a multi core chip

PLURALITY

ALU- Arithmetic operations[ADD, SUB]:

Here we will use a strategy that is similar to the strategy used in logical operations test, including more special cases(8) because of the Carry bit that we have.


Validation of a multi core chip

PLURALITY

ALU:

We will divide the ALU test to four parts :

Basic Arithmetic Operations

Shift operations

Logic Operations

Multiplier


Validation of a multi core chip

PLURALITY

ALU:

We will divide the ALU test to four parts :

Basic Arithmetic Operations

Shift operations

Logic Operations

Multiplier


Validation of a multi core chip

PLURALITY

ALU- Multiplier operation:

We adopt a determinist test strategy for multiplier-accumulator pairs. As it was proven theoretically and experimentally that this method achieves very high fault coverage.

The method takes two words X and Y, and focus on 4 bits of each word respectively. This way we can get 256 possibilities of multiplication values.


Validation of a multi core chip

PLURALITY

ALU- Multiplier operation:

The derived code achieves after compaction, the results

shown in the following Table for various architectures [3].

WORD LENGTH ARCHITECTUREFAULT COVERAGE

32 bits CSA - RCA 99.5%

32 bits CSA - CLA 99.3%

32bitsBWM - RCA 99.3%

32bitsBWM - CLA 99.2%

where CSA=cany save array multiplier, BWM=Booth

encoded tree (Wallace) multiplier, RCA=ripple-carry adder and CLA=canylookahead adder


Validation of a multi core chip

PLURALITY

Tests Block Diagram:

In this project we managed to divide the components to five categories :

Basic Test/Program Counter

ALU

FPU

Memory

Register file


Validation of a multi core chip

PLURALITY

Tests Block Diagram:

In this project we managed to divide the components to five categories :

Basic Test/Program Counter

ALU

FPU

Memory

Register file


Validation of a multi core chip

PLURALITY

FPU:

The FPU can be build in a lot of ways. Therefore we will assume that it is build according to IEEE standard(IEEE 754).

The FPU is a complexed unit, and under the lack of time that we have through this project, we can’t get a high fault coverage percentage.

Therefore we will run tens of small tests to test extreme cases such as : dividing by zero, overflow, etc…


Validation of a multi core chip

PLURALITY

Tests Block Diagram:

In this project we managed to divide the components to five categories :

Basic Test/Program Counter

ALU

FPU

Memory

Register file


Validation of a multi core chip

PLURALITY

Tests Block Diagram:

In this project we managed to divide the components to five categories :

Basic Test/Program Counter

ALU

FPU

Memory

Register file


Validation of a multi core chip

PLURALITY

Memory Testing:

Production tests objective is to verify that the device works correctly at speed throughout all the operation conditions.

In addition, maximum coverage and minimum time for execution are two main properties required for production test algorithms.

All of the existing memory test algorithms were developed based on their ability to detect functional faults.

Based on their complexities, simple algorithms such as zero-one and checkerboard tests are believed to be able to detect some simple functional faults such as the stuck-at fault. More complex algorithms, such as march 13N, can detect almost all the functional faults.


Validation of a multi core chip

PLURALITY

Memory Testing:

Explanation on memory faults :

Address Decoder Fault (AF) : A defect on the memory array, can happen within the address decoder or the read and write logic as well as on the row and column decoder.

Stuck At Fault (SAF) : The memory cell contains either a zero or a one all

the time and cannot change the state of the cell.

Transition Fault (TF) : The memory cell can change from one state to the

other but fails to go back to the initial state.


Validation of a multi core chip

PLURALITY

Memory Testing:

Explanation on memory faults :

Stuck-Open Fault (SOF) : In this case, the memory cell is not accessible by

either the write or read action.

Coupling Fault (CF) : Every time the memory cell is accessed by a write or

read, the content of the cells next to it change their values.

Data Retention Fault (DRF) : The memory cell loses its data after a certain

time.


Validation of a multi core chip

PLURALITY

Memory Testing [iv]:


Validation of a multi core chip

PLURALITY

Memory Testing:

We choose to implement two of these algorithms:

The first algorithm can locate only one of these faults – GALPAT - > GALROW.

The second algorithm can detect all of these faults- March 13N


Validation of a multi core chip

PLURALITY

Memory Testing:

GALPAT :

This algorithm is also known as Galloping 1/0 test.

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Validation of a multi core chip

PLURALITY

Memory Testing:

GALPAT :

The algorithm first initializes all memory cells to '0'.

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Validation of a multi core chip

PLURALITY

Memory Testing:

GALPAT :

Then, for each cell, it writes 'l', read all the cells and then writes back '0' to that cell.

32 31 ….. 4 3 2 1 0

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Validation of a multi core chip

PLURALITY

Memory Testing:

GALPAT :

Then, for each cell, it writes 'l', read all the cells and then writes back '0' to that cell.

32 31 ….. 4 3 2 1 0

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Validation of a multi core chip

PLURALITY

Memory Testing:

GALPAT :

The procedure looks like that a '1' is shifting its position from cell to cell throughout the whole memory.

32 31 ….. 4 3 2 1 0

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Validation of a multi core chip

PLURALITY

Memory Testing:

GALPAT :

The procedure looks like that a '1' is shifting its position from cell to cell throughout the whole memory.

32 31 ….. 4 3 2 1 0

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Validation of a multi core chip

PLURALITY

Memory Testing:

GALPAT :

The procedure looks like that a '1' is shifting its position from cell to cell throughout the whole memory.

32 31 ….. 4 3 2 1 0

0

0

0

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Validation of a multi core chip

PLURALITY

Memory Testing:

GALPAT :

The procedure looks like that a '1' is shifting its position from cell to cell throughout the whole memory.

32 31 ….. 4 3 2 1 0

0

0

1

0

0

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0

0

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N-1

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Validation of a multi core chip

PLURALITY

Memory Testing:

GALPAT :

The procedure looks like that a '1' is shifting its position from cell to cell throughout the whole memory.

32 31 ….. 4 3 2 1 0

0

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Validation of a multi core chip

PLURALITY

Memory Testing:

GALPAT :

The procedure looks like that a '1' is shifting its position from cell to cell throughout the whole memory.

32 31 ….. 4 3 2 1 0

0

1

0

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Validation of a multi core chip

PLURALITY

Memory Testing:

GALPAT :

The procedure looks like that a '1' is shifting its position from cell to cell throughout the whole memory.

32 31 ….. 4 3 2 1 0

1

0

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Validation of a multi core chip

PLURALITY

Memory Testing:

GALPAT :

The procedure looks like that a '1' is shifting its position from cell to cell throughout the whole memory.

32 31 ….. 4 3 2 1 0

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Validation of a multi core chip

PLURALITY

Memory Testing:

GALPAT :

In this algorithm each cell is read at least once, when it has a value '0' as well as when it has a value '1'. Thus, all cell stuck-at-l/O faults are detected.

The switching of state 0-to-1 and 1-to-0, also detects state transition faults.

As only one cell contains '1' at any time, and all cells are read, all address decoder faults are detected.

Any two arbitrary cells under state 00, 10 and 01 are read, this covers a majority of state coupling faults.


Validation of a multi core chip

PLURALITY

Memory Testing:

GALROW :

We will implement the GALROW algorithm that is based on GALPAT principle.

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Validation of a multi core chip

PLURALITY

Memory Testing:

GALROW :

In this algorithm, instead of shifting a '1' cell by-cell through the memory, a complete row of 1's is shifted. The whole memory is read after each shift.

32 31 ….. 4 3 2 1 0

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Validation of a multi core chip

PLURALITY

Memory Testing:

GALROW :

In this algorithm, instead of shifting a '1' cell by-cell through the memory, a complete row of 1's is shifted. The whole memory is read after each shift.

32 31 ….. 4 3 2 1 0

1

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Validation of a multi core chip

PLURALITY

Memory Testing:

GALROW :

In this algorithm, instead of shifting a '1' cell by-cell through the memory, a complete row of 1's is shifted. The whole memory is read after each shift.

32 31 ….. 4 3 2 1 0

0

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Validation of a multi core chip

PLURALITY

Memory Testing:

GALROW :

In this algorithm, instead of shifting a '1' cell by-cell through the memory, a complete row of 1's is shifted. The whole memory is read after each shift.

32 31 ….. 4 3 2 1 0

0

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Validation of a multi core chip

PLURALITY

Memory Testing:

GALROW :

In this algorithm, instead of shifting a '1' cell by-cell through the memory, a complete row of 1's is shifted. The whole memory is read after each shift.

32 31 ….. 4 3 2 1 0

0

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4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

111

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

GALROW :

In this algorithm, instead of shifting a '1' cell by-cell through the memory, a complete row of 1's is shifted. The whole memory is read after each shift.

32 31 ….. 4 3 2 1 0

0

0

0

0

0

0

0

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

111

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

GALROW :

The fault coverage of this algorithm is similar to GALPAT, except some state coupling faults. However, it is faster than GALPAT and requires n read/write operations.

3/2

In a variation, whole memory is not read after each shift, but only those cells are read which are supposed to contain '1'. This procedure is called as Shifting Row. This reduces the number of read/write operations to 4n.

However, state coupling faults and 50% of the state transition faults are not covered.

It should be noted that if shifting row is executed twice, once with a '0‘ background and second when background is 'l', majority of state transition faults and majority of state coupling faults will be covered.

The number of read/write operations will increase to 8n, which is still practical.


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N :

March 13N is an algorithm used as a production test. Therefore, its main purpose is to screen failing devices.

The meaning of "march l3N" is to march across the memory array with opposite states; zero or one, and access thirteen times each memory location;

detailed explanation is made in the algorithm skeleton :


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

32 31 ….. 4 3 2 1 0

-

-

-

-

-

-

-

-

0

1

2

3

4

.

.

.

N-2

N-1

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

1. First, Load the entire array with zeros “0”

32 31 ….. 4 3 2 1 0

0

0

0

0

0

0

0

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

First, Load the entire array with zeros “0”

32 31 ….. 4 3 2 1 0

0

0

0

0

0

0

0

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

Select the first word of the array.

Bit by bit perform the following operations :

32 31 ….. 4 3 2 1 0

0

0

0

0

0

0

0

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

2. read the zero “0”

32 31 ….. 4 3 2 1 0

0

0

0

0

0

0

0

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

3. Write a one “1”

32 31 ….. 4 3 2 1 0

0

0

0

0

0

0

1

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

4. Read a one “1”

32 31 ….. 4 3 2 1 0

0

0

0

0

0

0

1

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

32 31 ….. 4 3 2 1 0

0

0

0

0

0

0

1

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

32 31 ….. 4 3 2 1 0

0

0

0

0

0

1

1

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

32 31 ….. 4 3 2 1 0

0

0

0

0

0

1

1

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

32 31 ….. 4 3 2 1 0

0

0

0

0

0

1

1

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

32 31 ….. 4 3 2 1 0

0

0

0

0

1

1

1

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

32 31 ….. 4 3 2 1 0

0

0

0

0

1

1

1

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

32 31 ….. 4 3 2 1 0

0

0

0

0

1

1

1

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

32 31 ….. 4 3 2 1 0

0

0

0

1

1

1

1

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

32 31 ….. 4 3 2 1 0

0

0

0

1

1

1

1

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

32 31 ….. 4 3 2 1 0

1

1

1

1

1

1

1

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

Move to the next word of the array and perform operation described in

number three.

32 31 ….. 4 3 2 1 0

1

1

1

1

1

1

1

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

Move to the next word of the array and perform operation described in

number three.

32 31 ….. 4 3 2 1 0

1

1

1

1

1

1

1

0

1

2

3

4

N-2

N-1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

Move to the next words of the array and perform operation described in

number three.

32 31 ….. 4 3 2 1 0

1

1

1

1

1

1

1

0

1

2

3

4

N-2

N-1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

After finishing the entire array go back to the first word and perform operation

described in number three but with the opposite state 0<-->l.

32 31 ….. 4 3 2 1 0

1

1

1

1

1

1

1

0

1

2

3

4

N-2

N-1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

5. Read a one “1”

32 31 ….. 4 3 2 1 0

1

1

1

1

1

1

1

0

1

2

3

4

N-2

N-1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

6. Write a Zero “0”

32 31 ….. 4 3 2 1 0

1

1

1

1

1

1

0

0

1

2

3

4

N-2

N-1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

7. Read a Zero “0”

32 31 ….. 4 3 2 1 0

1

1

1

1

1

1

0

0

1

2

3

4

N-2

N-1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

Do to all Cells

32 31 ….. 4 3 2 1 0

0

0

0

0

0

0

0

0

1

2

3

4

N-2

N-1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

Once the whole array is check, select the last word of the array and perform the following operations bit-by-bit :

32 31 ….. 4 3 2 1 0

0

0

0

0

0

0

0

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

8. Read the Zero

32 31 ….. 4 3 2 1 0

0

0

0

0

0

0

0

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

9. Write a one “1”

32 31 ….. 4 3 2 1 0

0

0

0

0

0

0

0

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

10. Read a one “1”

32 31 ….. 4 3 2 1 0

0

0

0

0

0

0

0

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

32 31 ….. 4 3 2 1 0

0

0

0

0

0

0

0

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

32 31 ….. 4 3 2 1 0

0

0

0

0

0

0

0

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

32 31 ….. 4 3 2 1 0

0

0

0

0

0

0

0

0

1

2

3

4

N-2

N-1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

Once the whole array is checked, Repeat operation described in (5) to (7),

But with opposite states :

32 31 ….. 4 3 2 1 0

1

1

1

1

1

1

1

0

1

2

3

4

N-2

N-1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

11. Read a One “1”

32 31 ….. 4 3 2 1 0

1

1

1

1

1

1

1

0

1

2

3

4

N-2

N-1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

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1


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

12. Write a Zero “0”

32 31 ….. 4 3 2 1 0

1

1

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0

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N-2

N-1

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0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

13. Read a Zero “0”

32 31 ….. 4 3 2 1 0

1

1

1

1

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0

1

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N-2

N-1

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0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N [v] :

FINISHED WITH SUCCESS

32 31 ….. 4 3 2 1 0

0

0

0

0

0

0

0

0

1

2

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N-2

N-1

0

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0


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N :


Validation of a multi core chip

PLURALITY

Memory Testing:

March 13N :

Due to the fact that "march l3N" testing algorithm is designed as a production test,

execution time is a primary concern. Therefore, no debugging is performed when a

failure happens. In addition, each time the program fails to read the value stored, the

program will break and exit with the final value as FAIL. This is to ensure that the

devices that pass the memory testing algorithm are defective free concerning the memory

element that is checked by the algorithm.

Go back to tests Block Diagram


Validation of a multi core chip

PLURALITY

Tests Block Diagram:

In this project we managed to divide the components to five categories :

Basic Test/Program Counter

ALU

FPU

Memory

Register file


Validation of a multi core chip

PLURALITY

Tests Block Diagram:

In this project we managed to divide the components to five categories :

Basic Test/Program Counter

ALU

FPU

Memory

Register file


Validation of a multi core chip

PLURALITY

Register File Testing:

Register File and Memory fault are the same.

Therefore the Register File tests will be the same as the memory test algorithms.

This way we will check each one of the 32 registers on each CPU.

Click here to see memory faults and tests

Go back to tests Block Diagram


Validation of a multi core chip

PLURALITY

Basic script:

In order to make our work more efficient and make the implementation process more easy, we are going to write a basic script, “basic_test” Script, that is responsible for the compiling process with the needed files of the task map ,the task code file and where we want to run it (simulator / FPGA).

This test will run on one core.

For example :

>> basic_test –map_file“path_name” –task_file“path_name” -[sim] –[FPGA]


Validation of a multi core chip

PLURALITY

Final script:

  • The final script, is an easy way for a regular user to run our tests.

  • The output of that script is test_result.txt which includes conclusion of the tests results.

  • All he have to do is to run a command line with some options as detailed below :

  • This script will run the tests with few options :

  • which tests we want to run.

  • The cores that the tests are going to run on

  • Where we want to run the tests : Simulator/FPGA.

  • We will try to implement one more option:

  • Email notification when finishing the tests.

  • These option depends on cygwin capability.

  • For example :

  • >> Plurality_test –tests basic,ALU,memory_err_detect –cores 1,17-64 -[sim] –[FPGA] –email [email protected]


Validation of a multi core chip

PLURALITY

Gantt diagram:


Validation of a multi core chip

PLURALITY

References :

HyperCore Software Developer’s Handbook.

http://www.plurality.co.il/software/documents/SDH-draft-1.5.pdf

Deterministic Software-Based Self-Testing of Embedded Processor Cores, A. PASCHAUS D, Department of Informatics, University of Athens, Greece ,[email protected] .

Bret Pettichord, 2002, “Design for Testability”.

On Comparing Functional Fault Coverage and Defect Coverage for Memory Testing, Von-Kyoung Kim and Tom Chen

IMPROVED MICROPROCESSOR MEMORY TESTING ALGORITHM by CARLOS ENRIQUE CISNEROS, B.S.

vi.ALGORITHMS TO TEST PSF AND COUPLING FAULTS IN RANDOM ACCESS MEMORIES

RochitRajsuman, Dept. of Computer Engineering, Case Western Reserve University

Cleveland, OH 44106


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