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Automating HDL processing for the integration of hardware test and remote FPGA Laboratory

Automating HDL processing for the integration of hardware test and remote FPGA Laboratory. Presented by: David Newell Supervisor: Dr. Fearghal Morgan. Presentation Overview. Project overview. RFL demonstration. Goals. Text Parsing. File Editing. Designing for Test. Future work.

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Automating HDL processing for the integration of hardware test and remote FPGA Laboratory

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  1. Automating HDL processing for the integration of hardware test and remote FPGA Laboratory Presented by: David Newell Supervisor: Dr. Fearghal Morgan

  2. Presentation Overview • Project overview. • RFL demonstration. • Goals. • Text Parsing. • File Editing. • Designing for Test. • Future work.

  3. Project Overview • Project can be divided into two sections: • Section A: Automating the process of uploading VHDL code to the RFL website. • Section B: Automating the process of Design for Test integration. • Many of the concepts used in Section A will also be applied to Section B, such as text parsing and file editing. • The Java programming language is being utilised.

  4. What is the Remote FPGA Laboratory? • Is a resource for teaching digital systems. • RFL provides always-on access to FPGA boards. • Real-time demonstrations of digital system components. • http://remotefpga.com/app/l/635/#top

  5. Goals • Section A (RFL): • Reduce users’ workload when uploading VHDL designs to the RFL webpage. • Allow user to easily modify VHDL code, to increase observability of systems. • Automate the uploading of the VHDL files to RFL. • Section B (Analog Devices): • Reduce time to market by automating DfT of SoCs.

  6. Flow Chart • User input. • Parse desired files. • Extract signals. • Allow user to select internal signals to change to outputs. • Modify .vhd files. • Generate bit file. • Upload design to RFL.

  7. Parsing Text

  8. Java Regular Expression • Original plan was to use scanner method to extract signals. • This method was inefficient. • Regex is complicated to understand but very efficient. • Scans through line for pattern. • One downside is Regex is case sensitive.

  9. Editing .vhd files • To edit text files using Java the file must be temporarily stored before being edited. • New lines are entered into text file. • Modified file overwrites previous file, which did not include additional signals.

  10. IEEE 1500 • Main aim is to facilitate testing of embedded logic by creating additional circuitry around an embedded cores. • Extra hardware is added to each core. • Each core must include a WIR, WBY and a WBR.

  11. Future Work • The next stage of the project to be completed will be the GUI. • This will allow a prototype to be created and tested. • Automate bit file generation. • Allow user to select icons to display beside inputs and outputs on RFL webpage. • Determine if an exception list is required. • Automate design for test of SoCs.

  12. Questions

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