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EE 587 SoC Design & Test

EE 587 SoC Design & Test. Partha Pande School of EECS Washington State University pande@eecs.wsu.edu. System Design Issues. Low Energy FPGA Architecture. Architectural level optimization Level 0 – Nearest Neighbor Level 1 – Mesh Level 2 - Hierarchical. Different Architectures.

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EE 587 SoC Design & Test

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  1. EE 587SoC Design & Test Partha Pande School of EECS Washington State University pande@eecs.wsu.edu

  2. System Design Issues

  3. Low Energy FPGA Architecture • Architectural level optimization • Level 0 – Nearest Neighbor • Level 1 – Mesh • Level 2 - Hierarchical

  4. Different Architectures

  5. Paths in Interconnect • Connection may be long, complex: LE LE LE LE LE Wiring channel LE LE LE LE LE Wiring channel LE LE LE LE LE

  6. Interconnect Architecture • Connections from wiring channels to LEs. • Connections between wires in the wiring channels. Wiring channel LE LE

  7. channel channel channel channel Switchbox

  8. Mesh-based Interconnect Network Switch Box Routing of the data Connect Box Connects cell I/Os To the global interconnect InterconnectPoint Courtesy Dehon and Wawrzyniek

  9. Circuit Level Optimization • The connecting path from one CLB to another is an RCchain

  10. Low Swing Interconnect

  11. Low Power SRAM Design

  12. Memory Organization Bit line 2L-K Storage cell AK AK-1 AL-1 Word line M.2K Sense amplifiers/drivers A0 AK-1 Column decoder Input-Output (M bits)

  13. SRAM Cell VDD Precharge circuit PC EQ WL BL BL Output bit Sense amplifier bit

  14. Cell Array Power Management • Smaller transistors • Low supply voltage • Lower voltage swing (0.1V – 0.3V for SRAM) • Sense amplifier restores the full voltage swing for outside use.

  15. SRAM Cell Design • 6 transistor SRAM cell reduces static current (leakage) but take more area • Vth reduction in very low Vdd SRAMs suffer from large leakage current • Use multiple threshold devices: Memory cell with high Vth (reduce leakage) Peripheral circuits with low Vth (improve speed)

  16. Banked Organization • Banking targets total switched capacitance to achieve reduced power and improved speed

  17. Divided Word Line • Main idea: Divide each row of RAM cells into segments (blocks), use a decoder to access only one segment • Only the memory cells in the activated block have their bit line pair driven

  18. Divided Word Line • Pros: • Improves speed (by decreasing word line delay) • Lower power dissipation (by decreasing the number of bit line pair activated) • However, local decoders add delay • Less cells/block reduces power, but increases area (more local decoders) • Chang, 1997: 49.8% power reduction, 14.8% area penalty 82.9% power reduction, 24.8% area penalty

  19. Reduced Bit Line Swing • Limit voltage swing on bit lines to improve both speed and power: • Pulsed word line • Bit line isolation • Need sense amplifiers for each column to sense/restore signal

  20. Pulsed Word Line • Main idea: Isolate memory cells from the bit lines after sensing, to prevent the cells from changing the bit line voltage further

  21. Pulsed Word Line

  22. Pulsed Word Line • Dummy bit lines reach full swing, but trigger pulse shut off when regular bit lines reach 10% swing • Generation of word line pulses very critical • Too long: power efficiency degraded • Too short: Sense amplifiers operation may fail • Generation of word line using delay lines is susceptible to process and temperature

  23. Bit Line Isolation • Main idea: Isolate sense amplifiers from bit line after sensing, to prevent from having large voltage swings

  24. Row Decoders Collection of 2M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder

  25. Hierarchical Decoders Multi-stage implementation improves performance • • • WL 1 WL 0 A A A A A A A A A A A A A A A A 0 1 0 1 0 1 0 1 2 3 2 3 2 3 2 3 • • • NAND decoder using 2-input pre-decoders A A A A A A A A 1 0 0 1 3 2 2 3

  26. 1.30u 1.10u 0.13 m CMOS m 900n 700n Ileakage 500n Factor 7 300n 0.18 m CMOS m 100n 0.00 .600 1.20 1.80 VDD Data Retention in SRAM (A) SRAM leakage increases with technology scaling

  27. Reducing Retention Current • Turning off unused memory blocks • Increasing the thresholds by using body biasing • Inserting extra resistance in the leakage path • Lowering the supply voltage

  28. Suppressing Leakage in SRAM V DD V V low-threshold transistor DD DDL sleep V sleep DD,int V DD,int SRAM SRAM SRAM cell cell cell SRAM SRAM SRAM cell cell cell V SS,int sleep Inserting Extra Resistance Reducing the supply voltage

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