EE 587 SoC Design & Test. Partha Pande School of EECS Washington State University [email protected] SoC Physical Design Issues Wire Inductance. Wire Inductance. Wide wires in clock distribution & upper level metal layers These wires have low resistance
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SoC Physical Design Issues Wire Inductance
Z = R + jL
+

V
V=Ldi
i
dt
R
L
C
VO
Vin
VO = Zo Vin
R
L
C
Zt
Treat RC problem as a resistive divider:
1
sC
wn = 1/sqrt(LC)
z=RC/2sqrt(LC) = damping factor
Zo
=
Zt
1
sC
+ (R + sL)
wn2
1
=
=
s2 + s2zwn + wn2
s2LC + sRC + 1
z > 1 we have two real poles (RC effects)
z < 1 we have two complex poles (RLC effects)
Poles are P1,2 = wn [ z sqrt(z21)]
+

For most wires, jL < (Rwire+Rdrive) for the frequency and R of interest. So, for delay, L is not a big issue currently.
But L can be 20  30% of R so noise may be seen on adjacent line (mutual coupling)
Dangerous scenario is a combination
of localized capacitive coupling noise and
long range mutual inductive coupling noise
+ 
 +
Return path current
Double noise events
Rt=Rl, Lt=Ll, Ct=Cl, CT=CL/Ct
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Metal 2
Metal 1
Areawire
Areagate
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
Antenna
Ratio
=
Poly
This transistor could be damaged
1. CMP is chemical mechanical polishing which is used to planarize each layer before the next layer is placed on the wafer.
diodes costs area
 need to optimize number
and location
 causes problems for
design verification tool
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n+
p
Antenna diode
Should put antenna
diode here.
Keep area of upper layer metals
small near next transistor
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Metal 1/polish
vias (charge removed)
Metal2/polish
+ + + +