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CSC 3650 Introduction to Computer Architecture. Spring 2011. Time: 3:30 to 6:30. Meeting Days: W. Location: Oxendine 1237B. Textbook : Essentials of Computer Architecture , Author: Douglas E. Comer, 2005, Pearson Prentice Hall. Register Transfer Languages. Dr. Chuck Lillie.

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CSC 3650 Introduction to Computer Architecture

Spring 2011

Time: 3:30 to 6:30

Meeting Days: W

Location: Oxendine 1237B

Textbook: Essentials of Computer Architecture, Author: Douglas E. Comer, 2005, Pearson Prentice Hall

Register Transfer Languages

Dr. Chuck Lillie


Micro operations
Micro-operations

  • Micro-operations are the basis for most sequential digital systems

    • Movement of data from one register, memory location, or I/O device to another

    • Modify stored values

    • Perform arithmetic or logical functions

    • Modify a stored value

  • By performing a sequence of micro-operations to move and modify data, a sequential digital system performs a larger task


Hardware description language
Hardware Description Language

  • Used to design a system

    • More efficient than using digital logic

    • Used to verify that the logic of the design is correct

    • Can be translated into the final hardware design of the system

    • The design looks something like a computer program written in a high level language

    • Can be input into a circuit analysis and design (CAD) program to simulate the behavior of the circuit under all conditions


Implementation of the micro operation x y
Implementation of the micro operation X  Y

X

Direct Connection

Bus Connection

X  Y does not indicate the condition under which transfer occurs


Implementation of the data transfer x y
Implementation of the data transfer α: X  Y

X

Direct Path

Using a Bus

IF α THEN X  Y is written in RTL as α: X  Y


Implementation of data transfer x y y z
Implementation of Data Transfer α: X  Y, Y  Z

Single bus cannot be used because a bus can hold only one value at a time.

To improve system performance do two or more transfers simultaneously


Implementation of data transfer x y z y
Implementation of Data Transfer α: X  Y, Z  Y

Can write to more than one place at a time, but cannot send to the same location for more than one place

α: X  Y, Z  Y is OK

α: X  Y, X  Z is not OK


Three implementations of data transfers x 0 and x 1
Three implementations of data transfers α: X  0 and β: X  1

Move a constant value into a register

Using the CLR signal

Using a multiplexer to select data input

Using β as the data input

What happens if α and β are both 1?

1. Need hardware to ensure that will not happen or

2. Make sure they have mutual exclusion using one of the following three

α β’: X  0 α : X  0 α β’: X  0

β : X  1 α’ β :X  1 α’ β : X  1


Implementation of four bit data transfer x y
Implementation of four-bit Data Transfer α: X  Y

X

Direct Path

Using a Bus


Accessing single bits or subset of bits of multi bit register
Accessing single bits or subset of bits of multi-bit register

  • α: X(3-1)  Y(2-0)

  • β: X3  X2

  • : X(3-0)  X(2-0),X3 or X(2-0,3)




Transferring data between memory and registers
Transferring data between memory and registers register

  • To transfer between register AC and memory, first move address into address register and then perform transfer

    • AR  55

    • M[AR]  AC or AC  M[AR]

  • If decide AR is always the address register

    • M  AC and AC  M can be used without referring to AR


D flip flop
D flip-flop register

With clear input

Without clear input

LD: Q  D

CLR: Q  0

What happens when D, LD, CLR all 1

Need

CLR’ LD: Q  D LD: Q  D

CLR: Q  0 LD’ CLR: Q  0

Priority to CLR Priority to LD

LD: Q  D


Data paths of the system to implement the rtl code using direct connect
Data paths of the system to implement the RTL code using direct connect

j: M  A

o: A  Y

h: R  M

n: Y  R, M  R

What’s missing?



Implementation using bus with tri state buffers
Implementation using bus with tri-state buffers using direct connections

Advantage of bus over direct connect:

Bus system can be partitioned and their sections designed separately; task of buffer is not to pass the value of M on to the bus so it can be read in by register R, rather, its task is to place the contents of M on to the bus so that it can be read by whatever register should read it in.



State table for modulo 6 counter
State Table for Modulo 6 Counter using a bus and multiplexer

S0 S1  S2  S3  S4  S5  S0  …


State diagram for modulo 6 counter
State Diagram for Modulo 6 Counter using a bus and multiplexer

RTL code for the counter:

(S0 + S1 + S3 + S3 + S4)U: V  V + 1, C  0

S5U + S6 + S7: V  0, C  1

+ on left of : is OR, on right of : is arithmetic add












Vhdl code continued
VHDL code continued level of abstraction




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