CSC 3650 Introduction to Computer Architecture. Spring 2011. Time: 3:30 to 6:30. Meeting Days: W. Location: Oxendine 1237B. Textbook : Essentials of Computer Architecture , Author: Douglas E. Comer, 2005, Pearson Prentice Hall. CPU Design. Dr. Chuck Lillie. Generic CPU State Diagram.
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CSC 3650 Introduction to Computer Architecture
Spring 2011
Time: 3:30 to 6:30
Meeting Days: W
Location: Oxendine 1237B
Textbook: Essentials of Computer Architecture, Author: Douglas E. Comer, 2005, Pearson Prentice Hall
CPU Design
Dr. Chuck Lillie
Generic CPU State Diagram
FETCH1: AR ïƒŸ PC
FETCH2: DR ïƒŸ M, PC ïƒŸ PC + 1
FETCH3: IR ïƒŸ DR[7..6], AR ïƒŸ DR[5..0]
Fetch Cycle for Very Simple CPU
FETCH1: AR ïƒŸ PC
FETCH2: DR ïƒŸ M, PC ïƒŸ PC + 1
FETCH3: IR ïƒŸ DR[7..6], AR ïƒŸ DR[5..0]
Fetch and Decode Cycles for Very Simple CPU
ADD1: DR ïƒŸ M
ADD2: AC ïƒŸ AC + DR
JMP1: PC ïƒŸ DR[5..0]
AND1: DR ïƒŸ M
AND2: AC ïƒŸ AC ^ DR
INC1: AC ïƒŸ AC + 1
Complete State Diagram for Very Simple CPU
This diagram includes the data paths for all the operations
FETCH1: AR ïƒŸ PC
FETCH2: DR ïƒŸ M, PC ïƒŸ PC + 1
FETCH3: IR ïƒŸ DR[7..6], AR ïƒŸ DR[5..0]
ADD1: DR ïƒŸ M
ADD2: AC ïƒŸ AC + DR
AND1: DR ïƒŸ M
AND2: AC ïƒŸ AC ^ DR
JMP1: PC ïƒŸ DR[5..0]
INC1: AC ïƒŸ AC + 1
AR: AR ïƒŸ PC; AR ïƒŸ DR[5..0]
PC: PC ïƒŸ PC + 1; PC ïƒŸ DR[5..0]
DR: DR ïƒŸ M
IR: IR ïƒŸ DR[7..6]
AC: AC ïƒŸ AC + DR; AC ïƒŸ AC ^ DR; AC ïƒŸ AC + 1
Preliminary Register Section for the Very Simple CPU
Simple Observations:
AR only supplies its data to memory â€“ donâ€™t need to connect to any other component
IR does not supply data to any other component via the internal bus â€“ can remove output connection
AC does not supply itws data to any component â€“ remove connection to internal bus
The bus is 8 bits wide, but not all data transfers are 8 bits (some are 6, some are 2) â€“ need to specify which registers send and receive to and from which bus
AC must be able to load the sum of AC and DR, logical AND of AC and DR. CPU needs to include an ALU to do that.
Final Register Section for the Very Simple CPU
A Very Simple ALU
Create separate hardware for each function and use a multiplexer to select the function results
Generic Hardwired Control Unit
Hardwired Control Unit for Very Simple CPU
Control Signal Generation for Very Simple CPU
Fetch and Decode Cycles for Relatively Simple CPU
FETCH1: AR ïƒŸ PC
FETCH2: DR ïƒŸ M, PC ïƒŸ PC ïƒŸ PC + 1
FETCH3: IR ïƒŸ DR, AR ïƒŸ PC
JUMP1: DR ïƒŸ M, AR ïƒŸ AR + 1
JUMP2: TR ïƒŸ DR, DR ïƒŸ M
JUMP3: PC ïƒŸ DR, TR
JMPZY1: DR ïƒŸ M, AR ïƒŸ AR + 1
JMPZY2: TR ïƒŸ DR, DR ïƒŸ M
JMPZY3:PC ïƒŸ DR, TR
JMPZN1: PC ïƒŸ PC + 1
JMPZN2: PC ïƒŸ PC + 1
JPNZY1: DR ïƒŸ M, AR ïƒŸ AR + 1
JPNZY2: TR ïƒŸ DR, DR ïƒŸ M
JPNZY3:PC ïƒŸ DR, TR
JPNZN1: PC ïƒŸ PC + 1
JPNZN2: PC ïƒŸ PC + 1
LDAC1: DR ïƒŸ M, PC ïƒŸ PC + 1, AR ïƒŸ AR + 1
LDAC2: TR ïƒŸ DR, DR ïƒŸ M, PC ïƒŸ PC + 1
LDAC3: AR ïƒŸ DR, TR
LDAC4: DR ïƒŸ M
LDAC5: AC ïƒŸ DR
STAC1: DR ïƒŸ M, PC ïƒŸ PC + 1, AR ïƒŸ AR + 1
STAC2: R ïƒŸ DR, DR ïƒŸ M, PC ïƒŸ PC + 1
STAC3: AR ïƒŸ DR, TR
SRTAC4: DR ïƒŸ AC
STAC5: M ïƒŸ DR
MVAC1: R ïƒŸ AC
MOVR1: AC ïƒŸ R
ADD1: AC ïƒŸ AC + R, IF (AC + R = 0) THEN Z ïƒŸ 1 ELSE Z ïƒŸ 0
SUB1: AC ïƒŸ AC - R, IF (AC - R = 0) THEN Z ïƒŸ 1 ELSE Z ïƒŸ 0
INAC1: AC ïƒŸ AC + R, IF (AC + R = 0) THEN Z ïƒŸ 1 ELSE Z ïƒŸ 0
CLAC1: AC ïƒŸ 0, Z ïƒŸ 1
AND1: AC ïƒŸ AC ^ R, IF (AC ^ R = 0) THEN Z ïƒŸ 1 ELSE Z ïƒŸ 0
OR1: AC ïƒŸ AC | R, IF (AC | R = 0) THEN Z ïƒŸ 1 ELSE Z ïƒŸ 0
XOR1: AC ïƒŸ AC +| R, IF (AC +| R = 0) THEN Z ïƒŸ 1 ELSE Z ïƒŸ 0
NOT1: AC ïƒŸ AC`IF (AC` = 0) THEN Z ïƒŸ 1 ELSE Z ïƒŸ 0
Complete State Diagram for the Relatively Simple CPU
AR: AR ïƒŸ PC; AR ïƒŸ AR + 1; AR ïƒŸ DR, TR
PC: PC ïƒŸ PC + 1; PC ïƒŸ DR, TR
DR: DR ïƒŸ M, DR ïƒŸ AC
IR: IR ïƒŸ DR
R: R ïƒŸ AC
TR: TR ïƒŸ DR
AC: AC ïƒŸ DR; AC ïƒŸ R; AC ïƒŸ AC + R; AC ïƒŸ R;
AC ïƒŸ AC + 1; AC ïƒŸ 0; AC ïƒŸ AC ^ r; AC ïƒŸ AC | r;
AC ïƒŸ AC +| R; AC ïƒŸ AC`
Z: Z ïƒŸ 0 (both conditional)
Preliminary Register Selection for the Relatively Simple CPU
Need modifications:
AR and IR do not supply data to other components
Pins D[7..0] are bidirectional, but cannot output data from pins in current configuration
16-bit bus not fully used by al registers. Must specifiy which bits of data bus are connected to which bits of registers
Register Z not connected to anything
Generic Bidirectional Data Pin
Final Register Selection for the Relatively Simple CPU
LDAC5: AC ïƒŸ DR
MOVR1: AC ïƒŸ R
ADD1: AC ïƒŸ AC + R
SUB1: AC ïƒŸ AC - R
INAC1: AC ïƒŸ AC + R
CLAC1: AC ïƒŸ 0
AND1: AC ïƒŸ AC ^ R
OR1: AC ïƒŸ AC | R
XOR1: AC ïƒŸ AC +| R
NOT1: AC ïƒŸ AC`
LDAC5: AC ïƒŸ BUS
MOVR1: AC ïƒŸ BUS
ADD1: AC ïƒŸ AC + BUS
SUB1: AC ïƒŸ AC - BUS
INAC1: AC ïƒŸ AC + 1
CLAC1: AC ïƒŸ 0
LDAC5: AC ïƒŸ 0 + BUS+ 0
MOVR1: AC ïƒŸ 0 + BUS + 0
ADD1: AC ïƒŸ AC + BUS + 0
SUB1: AC ïƒŸ AC + BUS` + 1
INAC1: AC ïƒŸ AC + 0 + 1
CLAC1: AC ïƒŸ 0 + 0 + 0
Relatively Simple ALU
Hardwired Control Unit for the Relatively Simple CPU
Register Selection for the Relatively Simple CPU using Multiple Buses
Register Selection for the Relatively Simple CPU using Multiple Buses (cont)
Internal Organization of the 8085 Microprocessor
Page 260, Problem 6.1
Page 261,
Problem 6.2
Page 262, Problem 6.4
Page 262, Problem 6.4 Continued