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ECE122 – Lab 6 Latches & Flip-flops

The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering. ECE122 – Lab 6 Latches & Flip-flops. Jason Woytowich October 7, 2005. Latches & Flip-flops. Single bit memory elements

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ECE122 – Lab 6 Latches & Flip-flops

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  1. The George Washington UniversitySchool of Engineering and Applied ScienceDepartment of Electrical and Computer Engineering ECE122 – Lab 6 Latches & Flip-flops Jason Woytowich October 7, 2005

  2. Latches & Flip-flops • Single bit memory elements • Latches change state whenever the inputs dictate it • Flip-flops only change state on rising or falling clock edges

  3. SR Latch • Set/Reset Latch

  4. SR Latch • NOR Implementation

  5. SR Latch • NAND Implementation

  6. SR Latch

  7. D Latch • A Gated Latch

  8. D Latch • An SR Latch implementation

  9. D Latch

  10. D Flip-Flop • The value of D is stored on either the rising or falling clock edge. Clock D Q

  11. DFF • Master-Slave Implementation

  12. DFF

  13. DFF • Gate Trigger Implementation

  14. Positive Gate Trigger There are an odd number of inverters.

  15. Positive Gate Trigger

  16. DFF

  17. Lab Activities • Build and test an SR Latch from NAND Gates • Build and test a D Latch from the SR Latch • Build and test a DFF from your D Latch, MS or PGT

  18. Homework • Build a 4-bit incrementer • Put DFFs on the inputs and outputs • Find how fast you can drive the clock without producing errors

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