1 / 19

CENG 241 Digital Design 1 Lecture 7

CENG 241 Digital Design 1 Lecture 7. Amirali Baniasadi amirali@ece.uvic.ca. This Lecture. Chapter 5: Synchronous Sequential Logic. Sequential Circuits. There are two types of sequential circuits: Synchronous and Asynchronous. Synchronous Sequential Circuits. Synchronous Circuits:

ike
Download Presentation

CENG 241 Digital Design 1 Lecture 7

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. CENG 241Digital Design 1Lecture 7 Amirali Baniasadi amirali@ece.uvic.ca

  2. This Lecture • Chapter 5: Synchronous Sequential Logic

  3. Sequential Circuits There are two types of sequential circuits: Synchronous and Asynchronous

  4. Synchronous Sequential Circuits Synchronous Circuits: A system whose behavior can be defined from the knowledge of its signals at discrete instants of time Asynchronous Circuits: The output depends on the input signals at any instant of time and the order which inputs change

  5. Flip-Flops Sequential Circuits use flip-flops as storage elements Flip-Flop is a binary storage device that saves one bit of information The outputs can come from flip-flops or combinational logic Flip-flop inputs come from combinational logic or clock generators

  6. Latches Different flip-flops are different based on the number of inputs and how the inputs affect the binary state. Basic types of flip-flops operate with signal levels and are called latches. Example: SR latch

  7. SR Latches with NAND gates

  8. SR Latches with Control input S and R are allowed to change the flip-flop only when C = 1. If C=0, S and R can’t change output

  9. 1 1 1 D Latch Want to get rid of the undesirable SR condition where both S and R are 1. 0 1 0 1 1 1 0 Also called a transparent latch

  10. 1 1 1 D Latch Want to get rid of the undesirable SR condition where both S and R are 1. 1 0 1 1 0 0 1 Also called a transparent latch

  11. Graphic symbols for Latches

  12. FLIP-FLOPS Many flip-flops are edge triggered: They respond to the input only during transition from 0 to 1 or from 1 to 0.

  13. Edge-Triggered D Flip-Flop The output can change only when clock goes from 1 to 0. Data blocked here while CLK =1 1 1 1 0

  14. Edge-Triggered D Flip-Flop The output can change only when clock goes from 1 to 0. Data passes here while CLK =0 1 1 1 0 1

  15. 1 1 Positive Edge-Triggered D Flip-Flop How is this a positive edge triggered? Lets look at all possible scenarios: a) CLK = 0, then S=R=1 which causes the output to stay unchanged. 0

  16. 1 S used to be 1 when CLK was 0 1 1 1 0 Positive Edge-Triggered D Flip-Flop What if CLK goes from 0 to 1? (Positive-edge) a) D = 0, when CLK becomes 1, R changes to 0. Flip-Flop goes to reset state. Q=0. If D changes while CLK = 1, R remains 0. Q does not change. 1 0 1 0 Since one input is 0 changes in D can’t change Q 1

  17. 0 S and R used to be 1 when CLK was 0 1 1 1 1 1 0 Since one input is 0 changes in D can’t change Q 1 1 Positive Edge-Triggered D Flip-Flop What if CLK goes from 0 to 1? (Positive-edge) b) D = 1, when CLK becomes 1, S changes to 0. Flip-Flop goes to set state. Q=1. If D changes while CLK = 1, R remains 0. Q does not change. 1 1 0 1 0 0

  18. Graphic Symbols

  19. Summary • Latches, Flip-Flops: SR, D • Edge-triggered flip-flops

More Related