EECE 374: Microprocessor Architecture and Applications Chapter 2

1. EECE 374: Microprocessor Architecture and ApplicationsChapter 2

2. Agenda • Programming model • Memory addressing • Real-mode addressing • Protected-mode addressing • Memory paging • Flat mode memory

3. Programming Model • Set of registers to be used by the assembly programmer • General-Purpose Registers • Accumulator: al, ah, ax, eax • Others: bl, bh, bx, ebx, cl, ch, cx, ecx, dl, dh, dx, edx, bp, ebp, di, edi, si, esi • Special-Purpose Registers • Stack: sp, esp  meaning of stack • Instruction pointer: ip, eip • Flag register: flags, eflags • Segment registers Shaded area : from 80386

4. Accessing Registers with Different Sizes • A part of register can be accessed • Only rightmost 8/16/32 bits of 64b register are byte, word and double words Register size Override bits Accessed Example 8 bits B 7-0 MOV R9B, R10B 16 bits W 15-0 MOV R10W, AX 32 bits D 31-0 MOV R14D, R15D 64 bits - 63-0 MOV R13, R12

5. Multipurpose Registers

6. Special Purpose Registers

7. Flag Register C(carry) : holds the carry after addition or the borrow after subtraction P(parity) : 0 for odd, 1 for even parity A(auxiliary carry) : holds the carry or borrow between bit 3 and 4 Z(zero) : 1(result is 0), 0(result is not zero) S(sign) : 0(positive), 1(negative) T(trap) : enables trapping after each instruction for on-chip debugging I(interrupt) : enables(1) or disables(0) interrupt request from INTR pin D(direction) : increment(0) or decrement(1) of DI/SI for string instructions O(overflow) : out of range(1) of signed numbers operation

8. Examples of Flag Bits • Overflow V = C4 XOR C5 Scheme of Parallel Adder

9. Segment Registers

10. Code Relocation Issue 0000 1 0001 5 // # iterations 0010 -1 0011 5 // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 1011 … 1100 … 1101 … 1110 … 1110 … 0000 … 0001 … 0010 … 0011 … 0100 1 0101 5 // # iterations 0110 -1 0111 5 // result 1000 LD R1 0100 1001 LD R2 0101 1010 LD R3 0110 1011 ADD R0 R0 R1 1100 ADD R2 R2 R3 1101 BRNZ 1011 1110 ST 0111 R0 1111 … Addresses need to be changed on every code relocation

11. Memory Addressing • Real-mode addressing • 1MB address space • Only mode used in 8086 and 8088 microprocessors • Protected-mode addressing • Mode used to support a larger memory address space • Memory paging • Flat mode memory

12. An Example of Real-Mode Addressing Maximum address = FFFFF Segment = 1000 Offset = F000

13. Segments • Segment size = maximum 64KB • Segments can overlap with each other • Code Segment (cs) • Holds code to be executed • Data Segment (ds) • Holds general data used in the program • Other segments  es (for strings), fs, gs • Stack Segment (ss) • Holds data in a “default” location that can be accessed with “push” and “pop” instructions • LIFO (last-in-first-out) data structure

14. Segments 0000 1 0001 5 // # iterations 0010 -1 0011 5 // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0011 1010 ST 0011 R0 1011 … 1100 … 1101 … 1110 … 1110 … • Code Segment (cs) • Holds code to be executed • Data Segment (ds) • Holds general data used in the program • Other segments  es (for strings), fs, gs • Stack Segment (ss) • Holds data in a “default” location that can be accessed with “push” and “pop” instructions • LIFO (last-in-first-out) data structure DS CS

15. Real-Mode Addressing • Address = segment*10h + offset • Example: cs = 3034h, offset = 1234h • Address = (3034h) * (10h) + (1234h) = 31574h • Question (note: ds points to data segment): • ds = aabbh, offset = 432fh  address? 3034 cs: offset: + 1234 address: 31574

16. More Examples

17. Four Memory Segments Segments can be overlapped

18. Segments can be overlapped

19. Protected Mode Addressing • How to access 4GB (32b) memory space? • Segment register contains a selector that selects a descriptor from a descriptor table • The descriptor describes the memory segment’s location, length, and access rights

20. How to Access Memory Using a Descriptor

21. Contents of Segment Register • It selects one of 8192 descriptors from oneof two tables of descriptors (global and local descriptor tables) • Requested Privilege Level (RPL) requests the access privilege level of a memory segment. • If privilege levels are violated, system normally indicates an application or privilege level violation

22. How to Access Memory Using a Descriptor

23. Descriptors

24. Descriptors

25. How to Access Memory Using a Descriptor Why DS ranges 00100000H~ 001000FFH?

26. Descriptor Example 0 0 0 0 9 2 1 0 0 0 0 0 0 0 F F G = 0 Base = 00100000H Limit = 00FFH 00100000H~ 001000FFH

27. Descriptors (Cont’d) • The base address of the descriptor indicates the starting location of the memory segment • segments may begin at any address • The G, or granularity bit allows two granularities of segment length • G = 1  4KB granularity, G = 0  1B granularity • Example • Base=0H, Limit = FFFFFH • If G=0, memory segment can range between 0 and FFFFFH (1MB) • If G=1, it can range between 0 and FFFFFFFFH (4GB)

28. Access Rights in Descriptor

29. Program Invisible Registers

30. Program Invisible Registers (Cont’d) • Global and local descriptor tables are found in the memory system (with very long latency) • To access & specify the table addresses, 80286–Core2 contain program-invisible registers • Not directly addressed by software • Each segment register contains a program-invisible portion used in the protected mode • Often called cache memory because cache is any memory that stores information • Different from instruction/data cache!

31. Program Invisible Registers (Cont’d) • When a new segment number is placed in a segment register, the microprocessor accesses a descriptor table and loads the descriptor into the program-invisible portion of the segment register • held there and used to access the memory segment until the segment number is changed • This allows the microprocessor to repeatedly access a memory segment without referring to the descriptor table • hence the term cache

32. Memory Paging • The memory paging mechanism allows any physical memory location to be assigned to any linear address • Linear address is defined as the address generated by a program • Physical address is the actual memory location accessed by a program • With memory paging, the linear address is invisibly translated to any physical address

33. Memory Paging (Cont’d) • The linear address, as generated by software, is broken into three sections that are used to access the page directory entry, page table entry, and memory page offset address.

34. Paging Mechanism

35. Control Register

36. Address and Directory/Page Table Entry Address Entry in directory or page table

37. Paging Example • If the entry 0 of page table (of entry 0 of page table directory) contains address 00100000H, then • When the program accesses a location between 00000000H and 00000FFFH, the microprocessor physically addresses location 00100000H–00100FFFH 0 00100000H

38. Memory Paging (Cont’d) • Only one page directory in the system • The page directory contains 1024 doubleword addresses that locate up to 1024 page tables • Page directory and each page table are 4K bytes in length • Each entry in the page directory corresponds to 4M bytes of physical memory • Each entry in the page table repages 4K bytes of physical memory

39. Flat Memory

40. Flat Memory • A flat mode memory system is one in which there is no segmentation • does not use a segment register to address a location in the memory • First byte address is at 00 0000 0000H; the last location is at FF FFFF FFFFH • address is 40-bits • The segment register still selects the privilege level of the software

41. Flat Memory (Cont’d) • Real mode system is not available if the processor operates in the 64-bit mode • Protection and paging are allowed in the 64-bit mode • The CS register is still used in the protected mode operation in the 64-bit mode • Most programs today are operated in the IA32 compatible mode • current software operates properly, but this will change in a few years as memory becomeslarger and most people have 64-bit computers

42. Summary

43. Homework: Problems in Chapter 2 • To do: 7, 9, 27, 33, 43, 45 • 14, address for CS:IP • CS=1000H, IP=2000H  ?? • CS=3456H, IP=ABCDH  ??

44. Homework: Problems in Chapter 2 • To do: 7, 9, 27, 33, 43, 45 • 14, address for CS:IP • CS=1000H, IP=2000H  12000H • CS=3456H, IP=ABCDH  3F12DH

45. Problems in Chapter 2 • 26 • For an 80286 descriptor that contains a base address of A00000H and a limit of 1000H, what starting and ending locations are addressed by this descriptor? • 28 • For a Core2 (386-P4) descriptor that contains a base address of 00280000H, a limit of 00010H, and G=1, what starting and ending locations are addressed by this descriptor?

46. Problems in Chapter 2 • 26 • For an 80286 descriptor that contains a base address of A00000H and a limit of 1000H, what starting and ending locations are addressed by this descriptor? • A00000H-A01000H • 28 • For a Core2 (386-P4) descriptor that contains a base address of 00280000H, a limit of 00010H, and G=1, what starting and ending locations are addressed by this descriptor? • 00280000H-00290FFFH

47. Problems in Chapter 2 • 26 • For an 80286 descriptor of 000000A000001000H, what starting and ending locations are addressed by this descriptor? • 28 • For a Core2 (386-P4) descriptor of 0080002800000010H, what starting and ending locations are addressed by this descriptor?