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EECE 374: Microprocessor Architecture and Applications Chapter 1 (Part I)

EECE 374: Microprocessor Architecture and Applications Chapter 1 (Part I). Agenda (Chapter 1). Part I (3/13 and 3/15) 3/13 A minimum processor 3/15 Review on our minimum processor Bus Intel 4004 vs. our minimum processor Memory map Microprocessor performance improvement Part II (3/20)

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EECE 374: Microprocessor Architecture and Applications Chapter 1 (Part I)

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  1. EECE 374: Microprocessor Architecture and ApplicationsChapter 1(Part I)

  2. Agenda (Chapter 1) • Part I (3/13 and 3/15) • 3/13 • A minimum processor • 3/15 • Review on our minimum processor • Bus • Intel 4004 vs. our minimum processor • Memory map • Microprocessor performance improvement • Part II (3/20) • Number system • Multiplier and divisor

  3. Microprocessor • What is it? (Program Control Unit) (Data Processing Unit)

  4. Microprocessor • What is it? • What is the function of control, data path, memory, and input/output? • A minimum set of functions in microprocessor • Control: (un)conditional branch • Data path: addition of two numbers • Results: sum and status (e.g., zero, over/underflow) • Memory: read and write • Data is located with an address • Input/output

  5. A Minimum Microprocessor Binary format My first program 00 5 01 LD R2 00 10 ADD R3 R1 R2 11 BRNZ 01 00 00000101 01 10100000 10 01110110 11 00010000 *R1 is assumed to be initialized to zero =

  6. A Minimum Microprocessor Memory My first program LD R2 00, i.e., b10100000 00 5 01 LD R2 00 10 ADD R3 R1 R2 11 BRNZ 10 PC Control decode + branch Data path adder Registers R1,R2,R3 0 Zero *PC = program counter

  7. A Minimum Microprocessor Memory My first program Data at 00, i.e., b00000101 00 5 01 LD R2 00 10 ADD R3 R1 R2 11 BRNZ 10 PC Control decode + branch Data path adder Registers R1,R2,R3 5 Zero

  8. A Minimum Microprocessor Memory My first program 00 5 01 LD R2 00 10 ADD R3 R1 R2 11 BRNZ 10 Control decode + branch Data path adder Registers R1,R2,R3 PC 5 Zero 0 if the result is zero Zero = 1 else Zero = 0

  9. A Minimum Microprocessor Memory My first program 00 5 01 LD R2 00 10 ADD R3 R1 R2 11 BRNZ 10 Control decode + branch Data path adder Registers R1,R2,R3 PC Zero PC = 10 since Zero!=1

  10. A Minimum Microprocessor Memory My first program ADD R3 R1 R2, i.e., b00100000 00 5 01 LD R2 00 10 ADD R3 R1 R2 11 BRNZ 10 Control decode + branch Data path adder Registers R1,R2,R3 PC Zero We restart at 10 We do the same thing, R3=R1+R2=0+5 over and over again!

  11. A Minimum Microprocessor We need to increase the size of this field My first program! 00 5 01 LD R2 00 10 ADD R3 R1 R2 11 BRNZ 01 Too small code size! What if 4 bit address instead of 2 bits?

  12. A Minimum Microprocessor My first program! 0000 5 0001 LD R2 0000 0010 ADD R3 R1 R2 0011 BRNZ 0001 Let’s change my program to do something meaningful!

  13. A Meaningful Example Assumption R0 is initialized to 0 Assumption 1 integer = 1 byte 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 int a = 1; //  R1 int n = 5; //  R2 int d = -1; //  R3 int r = 0; //  R0 while(n!=0) { // BRNZ r = r + a; // R0=R0+R1 n = n + d; // R2=R2+R3 } Compiler!

  14. A Minimum Microprocessor Memory My first program LD R1 0000, i.e., b10 0001 0000 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 PC 0 1 Zero

  15. A Minimum Microprocessor Memory My first program LD R2 0001, i.e., b10 0010 0001 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 0 1 5 PC Zero

  16. A Minimum Microprocessor Memory My first program LD R3 0010, i.e., b10 0011 0010 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 0 1 5 -1 Zero PC

  17. A Minimum Microprocessor Memory My first program ADD R0 R0 R1, i.e., b01 0000 0001 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 1 1 5 -1 Zero PC

  18. A Minimum Microprocessor Memory My first program ADD R0 R0 R1, i.e., b01 0000 0001 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 1 1 4 -1 Zero 0 PC

  19. A Minimum Microprocessor Memory My first program BRNZ 0111, i.e., b00 0111 0000 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 1 1 4 -1 Zero 0 PC = 0111 since Zero != 1 PC

  20. A Minimum Microprocessor Memory My first program ADD R0 R0 R1, i.e., b01 0000 0001 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 2 1 4 -1 Zero 0 PC

  21. A Minimum Microprocessor Memory My first program ADD R0 R0 R1, i.e., b01 0000 0001 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 2 1 3 -1 Zero 0 PC

  22. A Minimum Microprocessor Memory My first program BRNZ 0111, i.e., b00 0111 0000 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 5 1 0 -1 Zero 1 PC After three more iterations …

  23. A Minimum Microprocessor Memory My first program BRNZ 0111, i.e., b00 0111 0000 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 5 1 0 -1 Zero 1 PC = 1010 since Zero=1 PC

  24. A Minimum Microprocessor Memory My first program ST R0 0011, i.e., b11 0011 0000 0000 1 0001 5 // # iterations 0010 -1 0011 5 // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 5 1 0 -1 Zero 1 PC

  25. Empirical Summary 0000 1 0001 5 // # iterations 0010 -1 0011 5 // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Address space

  26. Empirical Summary 0000 1 0001 5 // # iterations 0010 -1 0011 5 // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Data area Who decides data and code area? Code area

  27. Empirical Summary Your program! 0000 1 0001 5 // # iterations 0010 -1 0011 X // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 int a = 1; //  R1 int n = 5; //  R2 int d = -1; //  R3 int r = 0; //  R0 while(n!=0) { // BRNZ r = r + a; // R0=R0+R1 n = n + d; // R2=R2+R3 } Data area Code area Compiler!

  28. Empirical Summary Operation code OP code Instruction code Operands Register #, address

  29. What We Need to Know …In This Class • Op code • Given n instructions  log2n bits for Opcode. That’s all? • Operands • How to represent 64b address with 32b address field?  Addressing modes! • Control flow • How to execute function calls? • Data • Data types: how to represent a floating number, e.g., 3.14159… ? • Operation Addition is enough? Subtraction, multiplication, division, AND, OR, … • Memory allocation, e.g., malloc, free, … How do they work? • (Physical) memory • How to read/write data from/to memory? • Level 1 and 2 cache, DRAM, … What are they for? How do they work? • How to integrate all to make an instruction work? • Internal structure of microprocessor, e.g., address/data/control bus, I/O, … • Advanced topics • Interrupts, pipelining, branch prediction, DMA (direct memory access), SIMD and MMX, …

  30. Agenda (Chapter 1) • Part I (3/13 and 3/15) • 3/13 • A minimum processor • 3/15 • Review on our minimum processor • Bus • Intel 4004 vs. our minimum processor • Memory map • Microprocessor performance improvement • Part II (3/20) • Number system • Multiplier and divisor

  31. A Minimum MicroprocessorHow to Access Memory? Memory My first program LD R2 00, i.e., b10100000 00 5 01 LD R2 00 10 ADD R3 R1 R2 11 BRNZ 10 PC Control decode + branch Data path adder Registers R1,R2,R3 0 Zero Enough? How to tell memory to give me b10100000 at 0001? Contract with memory 1st cycle address, RD or WR = 1 2nd cycle data 8b Processor Memory RD WR

  32. A Minimum MicroprocessorHow to Access Memory? Memory My first program I want to read from 0001 00 5 01 LD R2 00 10 ADD R3 R1 R2 11 BRNZ 10 PC Control decode + branch Data path adder Registers R1,R2,R3 0 Zero 8b Cycle 1 0001 Processor Memory 1 RD WR 0

  33. A Minimum MicroprocessorHow to Access Memory? Memory My first program LD R2 00, i.e., b10100000 00 5 01 LD R2 00 10 ADD R3 R1 R2 11 BRNZ 10 PC Control decode + branch Data path adder Registers R1,R2,R3 0 Zero 8b Cycle 2 1010000 Processor Memory 0 RD WR 0

  34. A Minimum MicroprocessorWhat if You Want to See the Result? Memory My first program ST 0011 R0, i.e., b11 0011 0000 0000 1 0001 5 // # iterations 0010 -1 0011 5 // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 5 1 0 -1 Zero 1 PC

  35. A Minimum MicroprocessorNew Instruction for Output! Memory My first program OUT 0001 R0, i.e., b100 0001 0000 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 OUT 0001 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 5 Zero I/O device (I/O address = 0001) PC

  36. Bus System • Buses used in computer system • - Address bus • - Data bus • - Control bus • MWTC(memory write) • MRDC(memory read) • IOWC(IO write) • IORC(IO read)

  37. The Minimum Microprocessor is … • Similar to Intel 4004 (1971) Memory Control decode + branch Data path adder Registers R1,R2,R3 Zero

  38. Intel 4004 vs. Our Minimum Processor

  39. Intel 4004 • 4b data I/O

  40. Memory Space Comparison 4b 10b 4b address =16 entries of 10b data 12b address =4K entries of 4b data 4004 Ours

  41. Memory Access 4b Fetching an 8b instruction may take 8 cycles 10100000 1010 000011010001 0000 12b address =4K entries of 4b data 4b Cycle 1 0000 Processor Memory 1 RD WR 0 4004

  42. Memory Access 4b Fetching an 8b instruction may take 8 cycles 10100000 1010 000011010001 0000 12b address =4K entries of 4b data 4b Cycle 2 1101 Processor Memory 0 RD WR 0 4004

  43. Memory Access 4b Fetching an 8b instruction may take 8 cycles 10100000 1010 000011010001 0000 12b address =4K entries of 4b data 4b Cycle 3 0001 Processor Memory 0 RD WR 0 4004

  44. Memory Access 4b Fetching an 8b instruction may take 8 cycles 10100000 1010 000011010001 0000 12b address =4K entries of 4b data 4b Cycle 4 0000 Processor Memory 0 RD WR 0 4004

  45. Memory Access 4b 10100000 Fetching an 8b instruction may take 8 cycles 000011010010 1010 0000 12b address =4K entries of 4b data 4b Cycle 5 … 8 0000 Processor Memory 0 RD WR 0 4004

  46. Bus System • Buses used in computer system • - Address bus • - Data bus • - Control bus • MWTC(memory write) • MRDC(memory read) • IOWC(IO write) • IORC(IO read)

  47. Memory Access 4b Fetching an 8b instruction may take 8 cycles 10100000 1010 000011010001 0000 12b address =4K entries of 4b data 4b Cycle 1 0000 Processor Memory 1 RD WR 0 4004

  48. Memory Access 4b Fetching an 8b instruction may take 8 cycles 10100000 1010 000011010001 0000 12b address =4K entries of 4b data 4b Cycle 2 1101 Processor Memory 0 RD WR 0 4004

  49. Memory Access 4b Fetching an 8b instruction may take 8 cycles 10100000 1010 000011010001 0000 12b address =4K entries of 4b data 4b Cycle 3 0001 Processor Memory 0 RD WR 0 4004

  50. Memory Access 4b Fetching an 8b instruction may take 8 cycles 10100000 1010 000011010001 0000 12b address =4K entries of 4b data 4b Cycle 4 0000 Processor Memory 0 RD WR 0 4004

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