CDFG

1. CDFG 2012-04-12 謝政宏

2. CDFG void RGB_Y(I_Frame, O_Frame){ int y; for(int i=1; i<64; i++){ y = 0.257*a + 0.504*b + 0.098*c + 16; write(y) to O_Frame; } } ←1 01 system i I_P() I_P() I_P() 64 >= O01: i=1 O02: if(i>=64)goto O15 O03: a=I_P() O04: b=I_P() O05: c=I_P() O06: t1=0.257*a O07: t2=0.504*b O08: t3=0.098*c O09: t4=t1+t2 O10: t5=t3+16 O11: y=t4+t5 O12: O_P()=y O13: i++ O14: goto O02 O15: nop ← ← ← ++ a b c * 0.257 * 0.504 * 0.098 ← t1 t2 t3 + + 16 t4 t5 + y ← O_P()

3. Time constraint (C : 6 unit time) (R : 3* 2+) ←1 01 system i I_P() I_P() I_P() 64 >= ← ← ← ++ a b c * 0.257 * 0.504 * 0.098 ← t1 t2 t3 + + 16 t4 t5 + y ← O_P()

4. ←1 Resource constraint (C : 2* 1+ per unit time) (R : 7 unit time) 01 system i I_P() I_P() I_P() 64 >= ← ← ← ++ a b c * 0.257 * 0.504 ← 0.098 + * + 16 + ← O_P()

5. I_P() I_P() I_P() 1 I_P() I_P() I_P() 1 state0 state0 a b c a b c * * * * + + 0.257 0.504 -64 0.257 0.504 -64 state1 state1 o6 status o6 status v7 v7 + + o1 o2 1 o1 o2 state2 1 state2 o8 o8 v8 v8 v1 v2 v1 v2 + + * * 0.098 0.098 state3 state3 o3 o3 v3 v3 o6 + + o6 16 16 state4 state4 o4 o4 v4 v6 v4 v6 + + I_P() I_P() I_P() state5 I_P() I_P() I_P() state5 o5 o5 a b c a b c v5 v5 O_P() * * * * + + O_P() 0.257 0.504 -64 state1 0.257 0.504 -64 state1 o6 status o6 status v7 v7 + + o1 o2 1 o1 o2 state2 1 state2 o8 o8 v8 v8 v1 v2 v1 v2 + + * * 0.098 0.098 state3 state3 o3 o3 v3 v3 o6 + + o6 16 16 state4 state4 o4 o4 v4 v6 v4 v6 + + I_P() state5 I_P() I_P() I_P() I_P() I_P() state5 o5 o5 a b c a b c v5 v5 O_P() * * * * + + O_P() 0.257 0.504 -64 state1 0.257 0.504 -64 state1 o6 status o6 status v7 v7 + + o1 o2 state2 1 o1 o2 state2 1 o8 o8 v8 v8 v1 v2 v1 v2 + + * * 0.098 state3 0.098 state3 o3 o3 v3 v3 o6 + + o6 16 16 state4 state4 o4 o4 v4 v6 v4 v6 + + state5 state5 o5 o5 v5 v5 O_P() O_P()

6. loop body I_P() I_P() I_P() a b c * * + 0.257 0.504 -64 o6 status v7 + o1 o2 1 o8 v8 v1 v2 + * 0.098 o3 v3 + o6 16 o4 v4 v6 + o5 v5 O_P()

7. * mul1 = {o1} + * * + * mul2 = {o2, o6} + * + + add1 = {03, 04, 05, 07, 08} + R1 R1 = {v1, v3, v4} R2 R2 = {v2, v6} R3 R3 = {v8}

8. 0 1 0 1 0 1 0 1 0 1 0 1 2 3 datapath IP_B IP_C IP_A sel4 sel5 R1 R2 en1 en2 0.098 R3 0.257 0.504 -64 1 16 en3 sel1 sel2 sel3 * * + ==0 mul1 mul2 add1 status OP_Y

9. system clk rst IP_A IP_B IP_C controller datapath sel1 sel2 sel3 sel4 sel5 en1 en2 en3 status valid OP_Y

10. state table sel1=0 sel2=0 sel3=0 sel4=0 sel5=0 en1=0 en2=0 en3=0 rst=1 or status=1 state0 state5 state1 sel1=x sel2=1 sel3=2 sel4=x sel5=x en1=0 en2=0 en3=0 sel1=0 sel2=0 sel3=0 sel4=x sel5=x en1=0 en2=0 en3=0 state4 state2 sel1=1 sel2=1 sel3=3 sel4=1 sel5=0 en1=1 en2=1 en3=0 sel1=0 sel2=0 sel3=1 sel4=0 sel5=0 en1=1 en2=1 en3=1 state3 sel1=1 sel2=1 sel3=2 sel4=1 sel5=x en1=1 en2=0 en3=0 state table

11. datapath (1/3)

12. datapath (2/3)

13. datapath (3/3)

14. controller (1/2)

15. controller (2/2)

16. testbench (1/2)

17. testbench (2/2)

18. testbench2 (1/4)

19. testbench2 (2/4)

20. testbench2 (3/4)

21. testbench2 (4/4)

22. pre simulation (1/2)

23. pre simulation (2/2)

24. system

25. controller

26. datapath

27. datapath (zoom in)

28. system (synthesis)

29. post simulation (1/3)

30. post simulation (2/3)

31. post simulation (3/3)