Combinational circuits using vhdl
This presentation is the property of its rightful owner.
Sponsored Links
1 / 7

Combinational Circuits Using VHDL PowerPoint PPT Presentation


  • 76 Views
  • Uploaded on
  • Presentation posted in: General

Combinational Circuits Using VHDL. Contents. Combinational circuit examples: multiplexer using dataflow multiplexer using behavioral style decoder using structural style. Entity Definition for 4 to 1 Multiplexer. - - Define all necessary libraries library IEEE;

Download Presentation

Combinational Circuits Using VHDL

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Combinational circuits using vhdl

Combinational CircuitsUsing VHDL


Contents

Contents

  • Combinational circuit examples:

    • multiplexer using dataflow

    • multiplexer using behavioral style

    • decoder using structural style


Entity definition for 4 to 1 multiplexer

EntityDefinition for 4 to 1 Multiplexer

-- Define all necessary libraries

library IEEE;

use IEEE.STD_LOGIC_VECTOR_1164.all;

entity mux_4_to_1 is

port (S: in STD_LOGIC_VECTOR (1 downto 0); -- select vectorS(1:0)

A, B, C, D: in STD_LOGIC; -- inputs

Y: out STD_LOGIC);-- outputs

end mux_4_to_1;


Architecture for multiplexer using dataflow

Architecture for Multiplexer Using Dataflow

-- Note: S,A,B,C,D are defined in the entity definition

-- and will not be repeated here.

architecture mux_4_to_1_arch of mux_4_to_1 is

begin-- dataflow style (nocomponents orprocesses)

with S select Y <=

A when "00",

B when "01",

C when "10",

D when "11",

(others => 'U') when others; -- all possibilities are covered

end mux_4_to_1_arch;


Architecture for multiplexer in behavioral style

Architecture for Multiplexer in Behavioral Style

(Wakerely, p. 410)

-- Note: S,A,B,C,D are defined in the entity definition

-- and will not be repeated here.

architecture mux4in8p of mux_4_to_1 is

begin

process (S, A, B, C, D) -- execution if there is a change in S, A, B, C, orD.

begin -- All RHS variables and S are in the sensitivity list.

case S is

when "00" => Y <= A;

when "01" => Y <= B;

when "10" => Y <= C;

when "11" => Y <= D;

when others => Y <= (others => 'U'); -- all possibilities covered

end case;

end process;

end mux4in8p;


Decoder 2 to 4 in structural style

Decoder 2 to 4 in Structural Style (Ι/ΙΙ)

library IEEE;

use IEEE.std_logic_1164.all;

entity V2to4dec is

port (I0, I1, EN: in STD_LOGIC;-- two input selectors

Y0, Y1, Y2, Y3: out STD_LOGIC); -- four outputs

end V2to4dec;

architecture V2to4dec _s of V2to4dec is

signal NOTI0, NOTI1: STD_LOGIC; -- internal wires.

-- definition of required component (from IEEE)

component inv port (I: in STD_LOGIC;

O: out STD_LOGIC);

end component;


Combinational circuits using vhdl

Decoder 2 to 4 in Structural Style (ΙΙ/ΙΙ)

component and3

port (I0, I1, I2: in STD_LOGIC; O: out STD_LOGIC);

end component;

begin --inside the architecture, everything is executed in parallel

U1: inv port map (I0, NOTI0); -- can read inputs …

U2: inv port map (I1, NOTI1); -- and output to NOT10, NOT1

U3: and3 port map (NOTI0, NOTI1, EN, Y0); -- gate to outputs …

U4: and3 port map ( I0, NOTI1, EN, Y1);

U5: and3 port map (NOTI0, I1, EN, Y2);

U6: and3 port map ( I0, I1, EN, Y3);

end Vto4dec_s;


  • Login