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Digital Systems I

Digital Systems I. EEC 180A Lecture 4 Bevan M. Baas. m 0. Minterm Example. m 1. This circuit schematic shows all 8 minterms “present” for a 3-input combinational logic function In practice, all possible minterms would never all be present in a circuit (do you see why?)

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Digital Systems I

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  1. Digital Systems I EEC 180A Lecture 4 Bevan M. Baas

  2. m0 MintermExample m1 • This circuit schematic shows all 8 minterms “present” for a 3-input combinational logic function • In practice, all possible minterms would never all be present in a circuit (do you see why?) • There is one possible minterm for each row in the truth table m2 m3 Z m4 m5 m6 m7

  3. m0 MintermExample 0 0 0 1 m1 1 • By construction, one and only one minterm is active (equals 1) at any point in time m2 0 m3 0 1 Z m4 0 m5 0 m6 0 m7 0

  4. m0 MintermExample 1 0 0 1 m1 0 • By construction, one and only one minterm is active (equals 1) at any point in time m2 0 m3 0 1 Z m4 0 m5 1 m6 0 m7 0

  5. m0 MintermExample 1 0 0 1 m1 0 • Z = m0 + m1 + m7 • To implement an expression, a circuit is built with only the present minterm(s) • The output can be 1 only when one of the present minterms forces the output to 1 m2 0 Z m7 0

  6. m0 MintermExample 1 0 1 1 m1 0 • Z = m0 + m1 + m7 • To implement an expression, a circuit is built with only the present minterm(s) • The output can be 1 only when one of the present minterms forces the output to 1 m2 1 Z m7 1

  7. m0 MintermExample 1 0 1 1 m1 0 • Z = m0 + m1 + m7 • Of course gate inputs can not be left unconnected (unspecified). There are two solutions: • Tie unused inputs to a value that disables those inputs. For an OR gate, inputs would be tied to 0 (or False or Gnd) • The best solution is to simplify the gate. In this example, the 8-input OR gate is simplified to a 3-input OR gate m2 1 Z m7 1

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