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DRS2 Chip

DRS2 Chip. DRS2 chip designed 500 MHz – 5 GHz sampling speed 8+2 channels, 1024 bins deep each Readout speed up to 100 MHz (?) Submitted to UMC in Nov. 18 th , 58 chips received in Jan. 15 th , packaging 3 weeks Tests planned Feb. ‘04 – April ‘04

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DRS2 Chip

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  1. DRS2 Chip • DRS2 chip designed • 500 MHz – 5 GHz sampling speed • 8+2 channels, 1024 bins deep each • Readout speed up to 100 MHz (?) • Submitted to UMC in Nov. 18th, 58 chips received in Jan. 15th, packaging 3 weeks • Tests planned Feb. ‘04 – April ‘04 • Redesign only if problems (next submission April or June ‘04) • Board integration – July ’04 (PSI GVME board) • Full chip production run in fall ‘04

  2. DRS2 Chip Layout Readout shift register Domino Circuit Die: 5 x 5 mm ~250,000 Transistors Chip: PLCC 68 2 Test channels 10 channels x 1024 bins

  3. PSI GVME Board

  4. DRS (DAQ) 2002 2003 2004 2005 1st Prototype Tests 2nd Prototype Boards & Chip Test Design Manufactoring Assembly Test Milestone

  5. HV • Original design works +- 0.2V @ 2400V • Microcontroller crashes if HV load changes quickly • Redesign started in Nov. ’03 • 16-bit DACs, 24-bit ADCs • Faster microcontroller for 4 channels • HV part optically decoupled from uC • First prototype March ‘03

  6. Platform • CAD Design finished • Quotes for manufacturing • Ready for next beam time 7

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  9. MEG Sensitivity vs. Efficiency Proposal: Always show cut efficiency together with resolution AND its influence on MEG Branching Ratio Sensitivity

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