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CS 61C: Great Ideas in Computer Architecture Flip-Flops, FSMs , Logisim , Muxes

CS 61C: Great Ideas in Computer Architecture Flip-Flops, FSMs , Logisim , Muxes. Instructor: David A. Patterson http://inst.eecs.Berkeley.edu/~cs61c/sp12. You are Here!. Software Hardware. Parallel Requests Assigned to computer e.g., Search “Katz” Parallel Threads

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CS 61C: Great Ideas in Computer Architecture Flip-Flops, FSMs , Logisim , Muxes

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  1. CS 61C: Great Ideas in Computer Architecture Flip-Flops, FSMs, Logisim, Muxes Instructor: David A. Patterson http://inst.eecs.Berkeley.edu/~cs61c/sp12 Spring 2012 -- Lecture #18

  2. You are Here! Software Hardware • Parallel Requests Assigned to computer e.g., Search “Katz” • Parallel Threads Assigned to core e.g., Lookup, Ads • Parallel Instructions >1 instruction @ one time e.g., 5 pipelined instructions • Parallel Data >1 data item @ one time e.g., Add of 4 pairs of words • Hardware descriptions All gates @ one time • Programming Languages SmartPhone Warehouse Scale Computer HarnessParallelism & Achieve HighPerformance Today Computer … Core Core Memory (Cache) Input/Output Core Functional Unit(s) Instruction Unit(s) A3+B3 A2+B2 A1+B1 A0+B0 Cache Memory Logic Gates Spring 2012 -- Lecture #18

  3. lw $t0, 0($2) lw $t1, 4($2) sw $t1, 0($2) sw $t0, 4($2) Levels of Representation/Interpretation temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; High Level LanguageProgram (e.g., C) Compiler Anything can be representedas a number, i.e., data or instructions Assembly Language Program (e.g., MIPS) Assembler 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 Machine Language Program (MIPS) Machine Interpretation Hardware Architecture Description(e.g., block diagrams) Architecture Implementation Logic Circuit Description(Circuit Schematic Diagrams) Spring 2012 -- Lecture #18

  4. Review • Real world voltages are analog, but are quantized to represent logic 0 and logic 1 • Transistors are just switches, combined to form gates: AND, OR, NOT, NAND, NOR • Truth table can be mapped to gates for combinational logic design • Boolean algebra allows minimization of gates Spring 2012 -- Lecture #17

  5. Agenda • State Elements • Administrivia • Finite State Machines • Introduction to Logisim • Multiplexer • ALU Design • Summary Spring 2012 -- Lecture #18

  6. Type of Circuits • Synchronous Digital Systems consist of two basic types of circuits: • Combinational Logic (CL) circuits • Output is a function of the inputs only, not the history of its execution • E.g., circuits to add A, B (ALUs) • Last lecture was CL • Sequential Logic (SL) • Circuits that “remember” or store information • aka “State Elements” • E.g., memories and registers (Registers) • Today’s lecture is SL Spring 2012 -- Lecture #17

  7. Design Hierarchy system control datapath coderegisters stateregisters combinationallogic multiplexer comparator register logic switchingnetworks Spring 2012 -- Lecture #17

  8. Remember This?Conceptual MIPS Datapath Spring 2012 -- Lecture #17

  9. Uses for State Elements • Place to store values for some amount of time: • Register files (like $1-$31 on the MIPS) • Memory (caches, and main memory) • Help control flow of information between combinational logic blocks • State elements are used to hold up the movement of information at the inputs to combinational logic blocks and allow for orderly passage Spring 2012 -- Lecture #17

  10. Accumulator Example Why do we need to control the flow of information? SUM S Xi Want:S=0; for (i=0;i<n;i++) S = S + Xi Assume: • Each X value is applied in succession, one per cycle • After n cycles the sum is present on S Spring 2012 -- Lecture #17

  11. First Try: Does this work? Feedback No! Reason #1: How to control the next iteration of the ‘for’ loop? Reason #2: How do we say: ‘S=0’? Spring 2012 -- Lecture #17

  12. Second Try: How About This? Register is used to hold up the transfer of data to adder Square wave clock sets when things change High (1) High (1) High (1) Low (0) Low (0) Low (0) Rounded Rectangle per clock means could be 1 or 0 Roughtiming … Xi must be ready before clock edge due to adder delay Time Spring 2012 -- Lecture #17

  13. Model for Synchronous Systems • Collection of Combinational Logic blocks separated by registers • Feedback is optional • Clock signal(s) connects only to clock input of registers • Clock (CLK): steady square wave that synchronizes the system • Register: several bits of state that samples on rising edge of CLK (positive edge-triggered) or falling edge (negative edge-triggered) Spring 2012 -- Lecture #18

  14. n instances of a “Flip-Flop” Flip-flop name because the output flips and flops between 0 and 1 D is “data input”, Q is “data output” Also called “D-type Flip-Flop” Register Internals Spring 2012 -- Lecture #17

  15. Camera Analogy Timing Terms • Want to take a portrait – timing right before and after taking picture • Set up time – don’t move since about to take picture (open camera shutter) • Hold time – need to hold still after shutter opens until camera shutter closes • Time click to data – time from open shutter until can see image on output (viewfinder) Spring 2012 -- Lecture #18

  16. Hardware Timing Terms • Setup Time: when the input must be stable before the edge of the CLK • Hold Time: when the input must be stable after the edge of the CLK • “CLK-to-Q” Delay: how long it takes the output to change, measured from the edge of the CLK Spring 2012 -- Lecture #18

  17. FSM Maximum Clock Frequency • What is the maximum frequency of this circuit? Hint: Frequency = 1/Period Max Delay = Setup Time + CLK-to-Q Delay + CL Delay Spring 2012 -- Lecture #18

  18. Pipelining to Improve Performance: BEFORE (1/2) Timing… High (1) High (1) High (1) High (1) Low (0) Low (0) Low (0) Low (0) Note: delay of 1 clock cycle from input to output. Clock period limited by propagation delay of adder/shifter Spring 2012 -- Lecture #18

  19. Pipelining to Improve Performance (2/2) • Insertion of register allows higher clock frequency • More outputs per second Timing… Ready before clock edge: setup time Delay for Adder Combinational Logic Delay for Setup + Clk to Q Delay for Shifter Combinational Logic Delay for Setup + Clk to Q Spring 2012 -- Lecture #18

  20. Administrivia • Project 3, Part 2: Prefer March 25 or April 1? • Due Sunday April 1 • OK to turn it in Sunday March 25 or even Friday March 23 Spring 2012 -- Lecture #17

  21. Administrivia • Project 3, Part 2 due Sunday 4/1 • Thread Level Parallelism and OpenMP • Last homework due Sunday 4/8 • Project 4, Part 1 due Sunday 4/8; Part 2 4/15 • Design a 16-bit pipelined computer in Logisim • Labs 10 and 11 prepare for Project 4 • Lab 12 – Malloc/Free in C • Extra Credit due 4/22 – Fastest Matrix Multiply • Final Exam Wednesday 5/9 11:30-2:30PM Spring 2012 -- Lecture #18

  22. 1 son wanted to ride bike a “Century” Getting to Know Your Prof 1 son wanted to Sprint Triathlon • Swim 0.5 miles (0.75 km) • Ride bike 12.5 miles (20 km) • Run 3.1 miles (5 km) • 102.3 miles in 7:04 • Avg 15 MPH, Max 38 MPH Spring 2012 -- Lecture #18

  23. Agenda • State Elements • Administrivia • Finite State Machines • Introduction to Logisim • Multiplexer • ALU Design • Summary Spring 2012 -- Lecture #18

  24. Another Great (Theory) Idea:Finite State Machines (FSM) • You may have seen FSMs in other classes • Same basic idea • Function can be represented with a “state transition diagram” • With combinational logic and registers, any FSM can be implemented in hardware Spring 2012 -- Lecture #18

  25. Example: 3 Ones FSM FSM to detect the occurrence of 3 consecutive 1’s in the Input Draw the FSM … Assume state transitions are controlled by the clock: On each clock cycle the machine checks the inputs and moves to a new state and produces a new output … Spring 2012 -- Lecture #18

  26. Hardware Implementation of FSM Register needed to hold a representation of the machine’s state.Unique bit pattern for each state. + Combinational logic circuit is used to implement a function maps from present state (PS) and inputto next state (NS) and output. = The register is used to break the feedbackpath betweenNext State (NS) and Prior State (PS), controlled by the clock Spring 2012 -- Lecture #18

  27. PS Input NS Output 00 0 00 0 00 1 01 0 01 0 00 0 01 1 10 0 10 0 00 0 10 1 00 1 Hardware for FSM: Combinational Logic Can look at its functional specification, truth table form Truth table … Spring 2012 -- Lecture #18

  28. Agenda • State Elements • Administrivia • Finite State Machines • Introduction to Logisim • Multiplexer • ALU Design • Summary Spring 2012 -- Lecture #18

  29. Logisim • Free schematic capture/logic simulation program in Java • “A graphical tool for designing and simulating logic circuits” • Search and download version 2.7.1, online tutorial • ozark.hendrix.edu/~burch/logisim/ • Drawing interface based on toolbar • Color-coded wires aid in simulating and debugging a circuit • Wiring tool draws horizontal and vertical wires, automatically connecting to components and to other wires. • Circuit layouts used as "subcircuits" of other circuits, allowing hierarchical circuit design • Included circuit components: inputs and outputs, gates, multiplexers, arithmetic circuits, flip-flops, RAM memory Spring 2012 -- Lecture #18

  30. Logisim Wires • Blue wires: value at that point is "unknown” • Gray wires: not connected to anything • OK when in process of building a circuit • When finished => wires not be blue or gray • If connected, all wires should be green • Bright green a 1 • Dark green a 0 Spring 2012 -- Lecture #18

  31. Common Mistakes in Logisim • Connecting wires together • Using input for output • Connecting to edge without connecting to actual input • Unexpected direction of input Spring 2012 -- Lecture #18

  32. Data Multiplexer(e.g., 2-to-1 x n-bit-wide) “mux” Spring 2012 -- Lecture #18

  33. N Instances of 1-bit-Wide Mux How many rows in TT? Spring 2012 -- Lecture #18

  34. How Do We Build a 1-bit-Wide Mux (in Logisim)? s Spring 2012 -- Lecture #18

  35. 4-to-1 Multiplexer How many rows in TT? Spring 2012 -- Lecture #18

  36. Alternative Hierarchical Approach(in Logisim) Spring 2012 -- Lecture #18

  37. Subcircuits • Subcircuit: Logisim equivalent of procedure or method • Every project is a hierarchy of subcircuits Spring 2012 -- Lecture #18

  38. N-bit-wide Data Multiplexer (in Logisim + tunnel) “mux” Spring 2012 -- Lecture #18

  39. PS Input NS Output 00 0 00 0 00 1 01 0 01 0 00 0 01 1 10 0 10 0 00 0 10 1 00 1 Hardware for FSM: Combinational Logic Can look at its functional specification, truth table form Truth table … Spring 2012 -- Lecture #18

  40. PS Input NS Output 00 0 00 0 00 1 01 0 01 0 00 0 01 1 10 0 10 0 00 0 10 1 00 1 Hardware for FSM: Combinational Logic Alternative Truth Table format: list only cases where value is a 1.Then restate as logic equations using PS1, PS0, Input • NS0 = PS1PS0Input • NS0 = ~PS1~PS0Input • NS1 = PS1PS0Input • NS1 = ~PS1PS0Input • Output= PS1PS0Input • Output= PS1~PS0Input Output is 1 PS PS PS Input Input Input Truth table … 01 10 00 1 1 1 NS bit 0 is 1 NS bit 1 is 1 Spring 2012 -- Lecture #18

  41. Arithmetic and Logic Unit • Most processors contain a special logic block called “Arithmetic and Logic Unit” (ALU) • We’ll show you an easy one that does ADD, SUB, bitwise AND, bitwise OR Spring 2012 -- Lecture #18

  42. Simple ALU Spring 2012 -- Lecture #18

  43. Adder/Subtractor: One-bit adder Least Significant Bit Spring 2012 -- Lecture #18

  44. Adder/Subtractor: One-bit adder (1/2) … Spring 2012 -- Lecture #18

  45. Adder/Subtractor: One-bit Adder (2/2) … Spring 2012 -- Lecture #18

  46. + + + N x 1-bit Adders  1 N-bit Adder Connect Carry Out i-1 to Carry in i: b0 Spring 2012 -- Lecture #18

  47. Twos Complement Adder/Subtractor Spring 2012 -- Lecture #18

  48. Critical Path • When setting clock period in synchronous systems, must allow for worst case • Path through combinational logic that is worst case called “critical path” • Can be estimated by number of “gate delays”: Number of gates must go through in worst case • Idea: Doesn’t matter if speedup other paths if don’t improve the critical path • What might critical path of ALU? Spring 2012 -- Lecture #18

  49. Summary • Hardware systems made from Stateless Combina-tionalLogic and Stateful“Memory” Logic (Registers) • Clocks tell us when D-flip-flops change • Setup and Hold times important • We pipeline long-delay CL for faster clock cycle • Split up the critical path • Finite State Machines extremely useful • Use muxes to select among input • S input bits selects 2S inputs • Each input can be n-bits wide, indep of S • Can implement muxes hierarchically • Can implement FSM with register + logic Spring 2012 -- Lecture #18

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