Test and test equipment december 2012 hsin chu taiwan
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Test and Test Equipment December 2012 Hsin -Chu , Taiwan. Roger Barth. Chapter Content. Test Drivers & Challenges Test & Yield Learning Test Cost Concurrent/Adaptive Test 3D Device Test Test Technology Requirements Test parallelism DFx

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Test and test equipment december 2012 hsin chu taiwan

Test and Test Equipment December 2012Hsin-Chu, Taiwan

Roger Barth


Chapter content

Chapter Content

  • Test Drivers & Challenges

  • Test & Yield Learning

  • Test Cost

  • Concurrent/Adaptive Test

  • 3D Device Test

  • Test Technology Requirements

    • Test parallelism

    • DFx

    • Device types: Logic, Memory, RF/AMS, MEMS/Imaging/LCD drivers

    • Device handling (Handlers, Probers)

    • Device contacting (probecards and test sockets)

ITRS 2012 Test and Test Equipment – Hsin-Chu, Taiwan


2012 test contributors

2012 Test Contributors

Kenichi Anzou

Dave Armstrong

John Aslanian

Roger Barth

Yi Cai

KrishnenduChakrabarty

TapanChakraborty

SreejitChakravarty

Wendy Chen

William Chui

Steve Comen

Zoe Conroy

Adam Cron

Al Crouch

Ted Eaton

Stefan Eichenberger

Bill Eklow

Paul Emmett

Ira Feldman

Francois-Fabien Ferhani

Shawn Fetterolf

Paul Franzon

Piergiorgio Galletta

Anne Gattiker

Sandeep Goel

Kazumi Hatayama

Hirokazu Hirayama

Hisao Horibe

Shuichi Ito

Hongshin Jun

Masahiro Kanase

Rohit Kapur

Toshiaki Kato

Brion Keller

Ajay Khoche

Satoru Kitagawa

Marc Knox

Masashi Kondo

Ken Lanier

Lenny Leon

Marc Loranger

Erik Jan Marinissen

Peter Maxwell

Cedric Mayor

Teresa McLaurin

Milanjan Mukherjee

Takeshi Nagasaka

Masaaki Namba

Naoaki Narumi

Phil Nigh

Akitoshi Nishimura

Hermann Obermeir

Jayson Park

Mike Peng-Li

Frank Poehl

Chris Portelli-Hale

Bill Price

Herb Reiter

Mike Ricchetti

Michael Rodgers

Tomonori Sasaki

Keno Sato

Masayuki Sato

Yasuo Sato

Ryuji Shimizu

Yoichi Shimizu

Fumio Sonoda

Hiroyoshi Suzuki

Tetsuo Tada

Satoru Takeda

Steven Tilden

Erik Volkerink

Adam Wright

Yervant Zorian

ITRS 2012 Test and Test Equipment – Hsin-Chu, Taiwan


2012 table change highlights

2012 Table Change Highlights

  • Parallelism

    • Adjusted commodity DRAM to full wafer probing

  • Prober

    • 450mm production delayed from 2015  2017

  • Probing

    • Added wafer probing test frequencies (MPU, DRAM, NAND, LCD)

    • Added pad probing force for wirebond and bump

  • Logic

    • Refocused the table to provide solid ATE requirements

      • EDA suppliers heavily involved in table generation

    • Single ended signal performance increased

  • DFT

    • 1-2 year slip of some DFT implementations

  • RF table

    • Increase in the number of radio ports over time; some pull-ins

ITRS 2012 Test and Test Equipment – Hsin-Chu, Taiwan


Drivers

Drivers

  • Device trends

    • Bandwidth (# of signals and data rates)

    • Integration of emerging and non-digital CMOS technologies

    • Complex electrical and mechanical characteristics

    • 3 Dimensional silicon - multi-die and Multi-layer

    • Fault Tolerant Architectures and Protocols

  • Test process complexity

    • Device customization and traceability during the test process

    • Adaptive test and Feedback data for tuning manufacturing

    • Concurrent Test of IP Blocks

  • Economic Scaling of Test

    • Physical and economic limits of test parallelism

    • Managing (logic) test data and feedback data volume (Time and Storage)

    • Managing cost effectiveness of DUT interface hardware

ITRS 2012 Test and Test Equipment – Hsin-Chu, Taiwan


Increasing complexity

Increasing Complexity

  • 20122025 MPU & SoC

    • 30x increase in Transistors per die

    • 7x increase in total cores

  • Transistor use is consistent over time

    • Memory: ~83%

    • Cores:13%

~7x increase

~30x increase

ITRS 2012 Test and Test Equipment – Hsin-Chu, Taiwan


Test vector data volume compression

Test Vector Data Volume & Compression

ITRS 2012 Test and Test Equipment – Hsin-Chu, Taiwan

  • Managing test data volume and associated cost is a challenge

  • Flat MPU DV will approach petabits by 2030

    • 100x reduction possible with compression

  • SoC Flat DV will near 10 terabits

    • Potentially 10,000x reduction with compression


Multi die sip test cost components

Multi-die / SiP Test Cost Components

Highly Complex vs. single die

ITRS 2012 Test and Test Equipment – Hsin-Chu, Taiwan


Test cost survey update

Test Cost Survey Update

Test Cost Metrics

Cost per unit

% of total Product Cost

Cost per second

Cost per megabit

2009

2011

Future Cost Drivers

New Defects and Reliability problems

Test Requirements of packaging

Interfacing - NEW

Data (yield learning, traceability, test data) - NEW

Current Test Cost Drivers

ATE capital

Interface hardware

ATE utilization - NEW

Test program development

Test Time and Coverage

Future cost control Methods

Wafer-level At Speed testing

Advanced embedded instruments

Adaptive Test

New contacting technologies

In system testing - NEW

Built-in Fault Tolerance

Current cost control Methods

Test Parallelism

Structural Test & Scan

Compression/DFT/BIST/BOST

Adaptive Test

Concurrent Test

Wafer-level at-speed testing

ITRS 2012 Test and Test Equipment – Hsin-Chu, Taiwan


Difficult challenges

Difficult Challenges

  • Cost of Test and Overall Equipment Efficiency

    • Interface Hardware, setup/flex, lot sizes

  • Test Development gating volume production

    • Increasing device complexity -> more complex test development

  • Detecting Systemic Defects

    • Line width variations, dopant distributions, systemic process defects

  • Screening for reliability

    • Erraticor intermittent device behavior

    • Mechanical damage during the testing process

    • Multi-die stacks/TSV

ITRS 2012 Test and Test Equipment – Hsin-Chu, Taiwan


Future opportunities

Future Opportunities

  • Test Program Automation

    • Automatic generation of an entire test program

    • Tester independent test programming language

    • Resolve Mixed Signal test programming challenges

  • Diagnosis in the Presence of Data Compression

  • Simulation and Modeling

    • Seamless integration of CAD layout, simulation & modeling into the test process

    • Move to a higher level of abstraction with Protocol Aware test resources

    • Focused test generation based on layout, modeling, and adaptive feedback

  • Design for Self Test

ITRS 2012 Test and Test Equipment – Hsin-Chu, Taiwan


Test technique progression

Test Technique Progression

Novel self test and repair

techniques

System

Test

Structural Test

With Advanced

Compression

There has been significant test technique evolution over time to reduce test time and data volume

Cost of Test

More progress is required to get to the ultimate goal

Structural Test

With Compression

Structural

Test

Functional

Test

ITRS 2012 Test and Test Equipment – Hsin-Chu, Taiwan


Fault tolerance

Fault Tolerance

  • Known Good Devices  “Not Known Bad Devices”

    • Errors are okay…but must be dealt with

    • Concept is not new (redundancy, dynamic repair, BISR)

  • On die/system vs. off die/system fault tolerance

    • Smarter protocol aware testers for interface test

  • Dealing with non-deterministic data

ITRS 2012 Test and Test Equipment – Hsin-Chu, Taiwan


Adaptive test

Adaptive Test

  • Modified testing based on analysis of real-time results

  • Benefits

    • Fast Test Time Reduction

    • Fast yield learning

    • Lower cost

    • Higher Quality

  • Requires data infrastructure

    • Database

    • Analysis tools

    • Confidence

  • Implementationis evolving and custom

ITRS 2012 Test and Test Equipment – Hsin-Chu, Taiwan


3d device testing challenges

3D Device Testing Challenges

  • Die level test access to all die in the stack

    • Communication thru the top die in the stack

  • Test Flow / Cost / Resources

    • Test partitioning, non-traditional test structure

  • Die to Die Interactions

    • Signal routing thru another die

  • Debug / Diagnosis

  • DFT, design partitioning

  • Test data management, distribution, & security

  • Power management and implications

ITRS 2012 Test and Test Equipment – Hsin-Chu, Taiwan


2013 plans

2013 Plans

  • 3D / “Cube” device test

    • Test step insertion / flow for TSV

    • Managing power & heat

    • Singulated die/stack handling

    • Reliability wafer test requirements

  • DFT / BISx via new methods – New Focus Team

    • 3D devices

    • Eliminate digital test data and test programs

    • RF / AMS parametric testing

    • MEMS

  • Cost & adaptive test section updates

    • Concurrent test

  • System Test

  • CMOS image sensor testing

ITRS 2012 Test and Test Equipment – Hsin-Chu, Taiwan


Summary

Summary

  • 3D stacked devices will change test paradigms

    • The methods and approach seem available

    • Considerable work ahead to implement

  • Adaptive testing is becoming a standard approach

    • Significant test data accumulation, distribution, and analysis challenges

  • Fault tolerant device test presents a challenge

  • Managing cost is overall challenge

    • Industry is pulling in cost reduction methodology

ITRS 2012 Test and Test Equipment – Hsin-Chu, Taiwan


Thank you

Thank You!


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