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Technology Roadmap of INTEL’s Processors. July 2014. Table of Contents. Intel’s product line from Pentium to Ivy Bridge Above 100 nm node (Gate-First) Sub-100 nm nodes: 90 nm and 65 nm (Gate-First) 45 nm, 32nm and 22nm (Gate-Last, high-k & metal gates)

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Technology Roadmap of INTEL’s Processors

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Technology roadmap of intel s processors

Technology Roadmap

of

INTEL’s Processors

July 2014


Table of contents

Table of Contents

Intel’s product line from Pentium to Ivy Bridge

Above 100 nm node (Gate-First)

Sub-100 nm nodes:

90 nm and 65 nm (Gate-First)

45 nm, 32nm and 22nm (Gate-Last, high-k & metal gates)

Parameters related to “Technology Node”

Contacted Gate Pitch

6T SRAM Cell Size

Metal 1 Pitch

Future

What to expect NEXT?


Technology roadmap of intel s processors

Above 100 nm, Gate-First: Package (top & bottom)

0.35 µm

Intel Pentium

Microprocessor (200 MHz)

0.18 µm

Intel III Microprocessor

“Coppermine” (450 MHz)

0.13 µm

Intel III Microprocessor

“Tualatin” (1.26 GHz)


Technology roadmap of intel s processors

Above 100 nm, Gate-First: Die and Die markings

0.35 µm

Intel Pentium

Microprocessor (200 MHz)

0.18 µm

Intel III Microprocessor

“Coppermine” (450 MHz)

0.13 µm

Intel III Microprocessor

“Tualatin” (1.26 GHz)

7.1 mm x 11.1 mm = 79 mm2

10.3 mm x 12.3 mm = 126.7 mm2

10.8 mm x 12.6 mm = 136.1 mm2


Technology roadmap of intel s processors

Above 100 nm, Gate-First: SRAM at gate level

0.35 µm

Intel Pentium

Microprocessor (200 MHz)

0.18 µm

Intel III Microprocessor

“Coppermine” (450 MHz)

0.13 µm

Intel III Microprocessor

“Tualatin” (1.26 GHz)

All the SRAMS: P+ diffusions of the pull-down transistors have an “H” shape and each one is shared by two SRAM cells

Wordline and pull-down are 90˚ at each other and this consumes lot of space


Technology roadmap of intel s processors

Above 100 nm: Critical Parameters

The devices before 0.35 µm are not taken because previous two generations (0.6 µm and 0.8 µm) used BiCMOS process

The 0.25 µm node has been omitted to avoid clutter


Technology roadmap of intel s processors

Above 100 nm: Summary

In four generations (0.35 µm, 0.25 µm, 0.18 µm, 0.13 µm):

  • The die area shrunk from 136 to 79 mm2

  • The gate length reduced from 335 nm to 70 nm

  • The metal 1 pitch scaled down from 950 nm to 360 nm

  • The SRAM cell size decreased from 18.1 µm2 to 3.25 µm2

    Not all parameters scaled in the same proportion

    Intel moved towards sub 100 nm nodes with process-integration experience in

    Cu-interconnects and low-k materials

    By 130 nm node all the processors had a clock frequency in the range of 3 GHz


Technology roadmap of intel s processors

Sub 100 nm, Gate-First: Package (Top & Bottom)

90 nm

Intel Pentium IV, “Prescott”

(3 GHz)

65 nm

Intel Dual Core, “Xeon”

(3 GHz)

90 nm and 65 nm are two generations below 100 nm nodes, which used conventional gate structure with poly for gate electrode and oxide for gate dielectric

65 nm node was essentially a shrink of 90 nm

The most innovative part in 65 nm node was the introduction of dual core architecture


Technology roadmap of intel s processors

Sub 100 nm, Gate-First: Die and Die markings

90 nm

Intel Pentium IV, “Prescott”

(3 GHz)

65 nm

Intel Dual Core, “Xeon”

(3 GHz)

13.4 mm x 10.4 mm = 142 mm2

10.8 mm x 10.34 mm = 112 mm2


Technology roadmap of intel s processors

Sub 100 nm, Gate-First: SRAM at gate level

65 nm

Intel Dual Core, “Xeon”

(3 GHz)

90 nm

Intel Pentium IV, “Prescott”

(3 GHz)

The SRAM cell at diffusion changed from H_O structure to continuous regions of P-well for NMOS transistors and I shaped regions of N-well for PMOS transistors

Intel 65 nm node is 2nd generation of strain silicon technology

65 nm node adopted the same uniaxial strained approach as 90 nm node

Epitaxial SiGe film was employed for PMOS source-drains in 65 nm and 90 nm node

Up to 65 nm node, single patterning was only used


Technology roadmap of intel s processors

Sub 100 nm, Gate-Last: Package (Top & Bottom)

45 nm

Intel Core 2TM Extreme, “Penryn” (3 GHz)

22 nm

Intel Quadcore, “Ivy Bridge”

(3.3 GHz)

32 nm Intel Dual Core, “Clarkdale/Westmere”

(3 GHz)


Technology roadmap of intel s processors

Sub 100 nm, Gate-Last: Die and Die Markings

32 nm Intel Dual Core, “Clarkdale/Westmere”

(3 GHz)

22 nm

Intel Quadcore, “Ivy Bridge”

(3.3 GHz)

45 nm

Intel Core 2TM Extreme, “Penryn” (3 GHz)

12.2 mm x 8.5 mm = 104 mm2

19.6 mm x 8.0 mm =

112 mm2

9.2 mm x 8.2 mm = 75.4 mm2


Technology roadmap of intel s processors

Sub 100 nm, Gate-Last: SRAM at gate level

22 nm

Intel Quadcore, “Ivy Bridge”

(3.3 GHz)

45 nm

Intel Core 2TM Extreme, “Penryn” (3 GHz)

32 nm Intel Dual Core, “Clarkdale/Westmere”

(3 GHz)

The 6T SRAM cell has been the vehicle to define technology nodes

Cross couple PMOS and NMOS metal gates are connected at the side of the metal gate.

45 nm node uses double patterning with 193 nm dry lithography

32 nm node uses double patterning with 193 nm immersion lithography

22 nm node introduces fins and uses double patterning with 193 nm immersion lithography


Technology roadmap of intel s processors

Sub 100 nm, Gate-Last: Summary

Intel’s 45 nm process is the first to incorporate high-k metal gate (HKMG) technology. Their innovative process protects the high-k gate dielectric from polysilicon etch by depositing a TiN top interface layer (TIL) before polysilicon deposition and patterning.

PMOS channel stress is enhanced by removing the polysilicon dummy gates which is an enabling factor of the replacement metal gate process Intel used for the first time double patterning based on 193 nm dry lithography for critical layers and at the transistor gate level. Intel’s 32 nm was essentially a shrink of 45 nm node with the exception that immersion lithography was used.

As of today, 2014, Intel is the only manufacturer to use a FinFET for its transistors. Intel 22 nm replaced the traditional 2-D planar MOS transistor with a gate that is wrapped around a thin three-dimensional silicon fin that rises up vertically from the silicon substrate . A thin high-k dielectric separates the silicon fin from the metal gate on each of the three sides of the fin


Technology roadmap of intel s processors

Sub 100 nm, Gate-Last: Graphical Summary


Technology roadmap of intel s processors

Sub 100 nm: Critical Dimensions (Logic)

90 nm and 45 nm have the same gate-length

65 nm and 32 nm have the same gate-length

Gate length is not an accurate parameter for defining technology node for devices below 100 nm node


Technology roadmap of intel s processors

Sub 100 nm: Critical Dimensions (SRAM)

The 32 nm node introduced the metal 0 level and changed the wiring position of bitlines (BL),

Wordlines (WL), Vss and Vdd lines and improved slightly the width/length (W/L) ratio of transistors

The SRAM in 22 nm node kept the same wiring configuration for BL, WL, Vdd and Vss, as

in 32 nm node but by introducing Tri-Gate (FinFET) structure improved W/L ratio

Generally, the widths of pull down transistors are greater than the widths of access transistors. The current ratio of I PD /I AC reflecting geometric device dimension is known as beta ratio. A higher beta ratio reflects higher cell stability


Table of contents1

Table of Contents

  • Intel’s product line from Pentium to Ivy Bridge

  • Above 100 nm node (Gate-First)

  • Sub-100 nm nodes:

  • 90 nm and 65 nm (Gate-First)

  • 45 nm, 32nm and 22nm (Gate-Last, high-k & metal gates)

  • Parameters related to “Technology Node”

  • Contacted Gate Pitch

  • 6T SRAM Cell Size

  • Metal 1 Pitch

  • Future

  • What to expect NEXT?


Technology roadmap of intel s processors

Parameters related to “Technology Node”

For advanced nodes “Gate-Length” is not a reliable parameter for defining technology node


Technology roadmap of intel s processors

Parameters related to “Technology Node”

The “Contacted Gate Pitch” takes in account the gate length and the minimum litho-features, thus reflects the actual technology node

“Contacted Gate Pitch” decreases by 0.7 every two years, following Intel’s “Tick Tock” scheme

Every alternate year Intel develops a new process technology and the following year a new

micro-architecture, (Tick / Tock scheme)


Technology roadmap of intel s processors

Parameters related to “Technology Node”

The “square root of 6T-SRAM cell area” is linear with technology node and is an accurate method to determine the technology node

Intel 22 nm has 0.092 µm2 SRAM cell for high density applications but our analysis did not locate these cells, only 0.108 µm2 SRAM cell for low voltage applications was found in reverse engineering.


Technology roadmap of intel s processors

Parameters related to “Technology Node”

The “Metal 1 Pitch” is also indicative of the technology node but not very accurate


Table of contents2

Table of Contents

  • Intel’s product line from Pentium to Ivy Bridge

  • Above 100 nm node (Gate-First)

  • Sub-100 nm nodes:

  • 90 nm and 65 nm (Gate-First)

  • 45 nm, 32nm and 22nm (Gate-Last, high-k & metal gates)

  • Parameters related to “Technology Node”

  • Contacted Gate Pitch

  • 6T SRAM Cell Size

  • Metal 1 Pitch

  • Future

  • What to expect NEXT?


Technology roadmap of intel s processors

What is coming NEXT?

  • Intel has developed both CPU and SoC processes for its 45 nm, 32 nm and 22 nm technology nodes

  • SoC products usually incorporate a variety of devices that are often not seen in regular CPU products

  • Intel will use the 22 nm technology node platform and diversify for different products

  • Intel is not pursuing only high performance, but developing process and architectures for wider range of products varying from server-market to mobile market

  • This wide variety of products requires different design at one particular technology node


Technology roadmap of intel s processors

What is coming NEXT?

  • Different chips with different designs are available at 22 nm technology, for example:

    • Ivy Bridge ( CPU);

    • Haswell (SoC);

    • Bay Trail (for tablets, Atom Z300 series)

Bay Trail 22 nm

ATOM Z300

Intel 22 nm

Haswell

Intel 22 nm

Ivy Bridge


Technology roadmap of intel s processors

What is coming NEXT?

Generation of High-K and Metal Gates with “Gate-Last” process

Most likely bulk FinFET will be used for 14 nm node

EUV will probably be used for sub 10 nm nodes


Technology roadmap of intel s processors

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