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A low-noise low-voltage continuous-time SD modulator with digital compensation of excess loop delay

A low-noise low-voltage continuous-time SD modulator with digital compensation of excess loop delay. Dr.S.Mehdi Fakhraie By: Mehrdad Ghobady. Outline. Introduction Quantization Error and Oversampling Decimation Process Delta Modulation Sigma-Delta Modulation

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A low-noise low-voltage continuous-time SD modulator with digital compensation of excess loop delay

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  1. A low-noise low-voltage continuous-time SD modulator with digital compensation of excess loop delay Dr.S.Mehdi Fakhraie By: Mehrdad Ghobady

  2. Outline • Introduction • Quantization Error and Oversampling • Decimation Process • Delta Modulation • Sigma-Delta Modulation • Sigma-Delta Modulator Architecture • Performance Summary • References

  3. Introduction • The performance of digital signal processing and communication systems is generally limited by the precision of the digital input signal which is achieved at the interface between analog and digital information. • Sigma - delta modulation based analog -to- digital (A/D) conversion technology is a cost effective alternative for high resolution (greater than 12 bits)converters which can be ultimately integrated on digital signal processor ICs.

  4. Fig.1:Compare of Speed and Resolution[3]

  5. Fig.2:Conventional Analog-to-Digital Conversion Process[2]

  6. Fig.3:Spectra of Analog and Sampled Signals[2]

  7. Quantization Error and Oversampling • Nyquist rate A/D converter • Oversampling A/D converter Fig.4:Frequency Response of Analog Anti-Aliasing Filters[2]

  8. Decimation Process Fig.5:Simple Example of Decimation Process[2]

  9. Delta Modulation Fig.6:Delta Modulation and Demodulation[2]

  10. Sigma-Delta Modulation Fig.7:Derivation of Sigma-Delta Kodulation from Delta Modulation[2]

  11. Sigma-Delta Modulation Fig.8:Block Diagram of Sigma-Delta Modulation[2]

  12. S-Domain Analysis of Sigma Delta Modulator Fig.9:S-Domain Analysis[2]

  13. Block Diagram of First-Order Sigma-Delta A/D Converter Fig.10:First-Order Sigma-Delta Converter[2]

  14. Sigma-Delta Modulator Architecture Fig.11:Sigma-Delta Modulator Architecture[1]

  15. The noise transfer function (NTF) has a pair of complex zeros judiciously chosen to maximize the SQNR in the bandwidth of interest ,and created by the local feedback. • The poles of the modulator (coefficients ai) represent 3rt order approximation. • Feedforward paths (coefficients bi) are used to reduce the dynamics at the output of the first integrator ,thus improving the overall linearity of the modulator.

  16. Performance Summary Table.1:Performance Summary of Sigma-Delta Modulator[1]

  17. References • [1] Paul Fontaine, Ahmed N.Mohieldin , Abdellatif Bellaouar ,” A Low-Noise Low-Voltage CT Delta-Sigma ModulatorWithDigital Compensation of Excess Loop Delay, “ JSSCC 2005. • [2] Sangil Park , “ Principles of Sigma-Delta Modulation for Analog-to-Digital Convertors” , MOTOROLA. • [3] David Jarman , “A Brief Introduction to Sigma-Delta Conversion” ,1995.

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