Update on Pixel Module Interfaces Mauro Citterio On behalf of INFN Milano

1. Update on Pixel Module Interfaces Mauro Citterio On behalf of INFN Milano

2. Layer 0 • Baseline: • SuperB SVT  similar to BaBar SVT +Layer 0 • Layer 0 technology to be chosen between maps, striplets or thin pixels • Each SVT layer is built of indepedent “modules” (52+8) • One module is divided in two independent “half modules” • Each half modules contains several “units”: • Sensor • Front-end chips • Interfaces (BUS and HDI) with power/signal input and data output link SVT System Integration Required for System Integration

3. Half Module: 6 MAPS Carbon Fiber Support BUS • Baseline: • Layer 0 BUS design derived by previous CERN experience with ALICE bus • High signal trace density  ~ 200 signal lines (MAPS case) • Minimum thickness maximum thickness ~ 220 mm • Sensor/readout interconnection  by wire bonding • Prototype: • The technical data from CERN need to be verified using a “simplified” structure • Various solutions on the same BUS • To compare simulation and actual BUS • To test the technological limits A “simplified bus”

4. What is in the prototype (1.8 x 11.2 cm): • Four layers  Stackup made of: Aluminum, polimide and glue • 2 planes (each 50 mm thick), power and ground • 2 signal layers + vias between the two layers • Min Pads/Vias 150/50 mm • Line widht: Min. ~ 75 mm, Max. 200 mm • Lines with different overall lenghts, with and without bends • Striplines and microstrips • Differential lines A “simplified bus”

5. Microstrip Striplines Purple: top layer Orange: bottom layer Power/ground planes: not shown Diff. lines A “simplified bus” • Dielectrics (polyimide + glue): 20 mm, 50 mm for 1st signal layer • Impedance • calculated to be 50 W in respect to first signal layer • lenght of top layer lines negligible  for impedance matching • No “accurate” models for vias

6. Data generated with CERN input … still evolving • The dielectric thickness adjusted to increase Z • Line widht is at the “nominal” minimum • Line space could be reduced (~ 50 mm) but does not affect Z, it increases NEXT Impedance simulation Not minimum thickness • The “plane layers” are 50 mm  suggested by CERN to improve yield • Because we would like to operate at ~ 160-180 MHz, aluminum signal lines will be plated by 2-3 mm of copper  overall thickness of lines estimated to be ~ 13 mm • Total thickness of prototypes is 140 mm less than FINAL BUS

7. Vertical lines 300 m for bonding on each bus side Horizontal signal lines Horizontal signal lines Glue 5µ Analogue ground 346 µ Polyimide 15µ Analogue power Aluminium 50µ Aluminium 13µ Digital power supply Aluminium 13µ Digital ground • Not an “enclosed stackup”: • Power plane must be on bottom • Signal lines are assumed to be microstrips • Better for speed, “high” impedance. • Worse for far-end crosstalk and EMC • If 200 signal lines needed  Three signal planes (two horizontal, one vertical) Using CERN "design rules" Updated estimate of final bus

8. If we use minimum dielectric thickness (15 mm) between signal layer and ground  the impedance drops to 30 W (w= 75 mm, w/h ~ 3.3, t << w) Z too low for being useful A “Simplified Bus”

9. To study the performance of the Bus, we have simulated the signal propagation using XILINX VIRTEX-5 driver and receiver: • for which IBIS models are available • because we plan to use these FPGAs in our test setup. • In the figure an “ideal” scenario is shown: • No bus • Direct connection between driver and receiver • Two overlapping signals are shown • The signal has180 MHz frequency and 49 % duty cycle • The shape is “extracted” by means of the IBIS models • The driver sends out a 1.2 Volt signal Signal Simulations with Hyperlinx

10. The bus is simulated by importing the stackup information An end of line termination, matching the impedance, is used The signal at the driver output is the “yellow” line The signal at the receiver input is the “blue” line The signal at the receiving end can still be read by the bus (logic level are matched) The simulation will be compared against real measurement as soon as we will have the “prototype bus” Signal Simulations: 50 Ohm BUS

11. Eye Diagram simulation: 50 Ohm BUS

12. The bus is simulated by importing the stackup information • An end of line termination, matching the impedance, is used • The signal at the driver output is the “yellow” line • The signal at the receiver input is the “blue” line • The signal at the receiving end can NOT be read by the bus • it does not reach the High logical level • Once again the design of a minimum thickness bus MUST be dropped Signal Simulations: 30 Ohm BUS IMPEDANCE TOO LOW

13. Simulation consider one aggressor and one victim nearby. Signal on victim is approximately 30 mV at its peak NEXT ~ 3 % NEXT simulation: 50 Ohm BUS

14. Layout of proto-BUS  almost completed • To be accepted by CERN next week (Rui De Oliveira) • The prototype will allow us to measure most of the “critical parameters” • A measurement setup is under design, it will use adapter cards to connect Xilinx FPGAs to the BUS Production of the prototype is expected in 8-10 weeks • The ball park figure is 6 KCHF • 10 pieces is the minimum quantity for the run. Ongoing Activity

15. Unspecified parameters • For a realistic layout, PADs position on chip must be defined • Evaluation of clock skew • No “decoupling” on the BUS • What is the tolerable Jitter • Driver to be implemented in the IC must be able to load a 50 W bus • ...... • ...... • Power distribution: • What is the tolerable drop on the power planes? • Can we use a single power plane? • by splitting it in two  substantial reduction in bus thichness (~ 70 mm) Still to be defined for a next version of the BUS

16. Hybrid Dimension (~ 13 mm x 70 mm x 15 mm)  for two optical links (total data rate ~ 10 Gbps) • Some space need to connect hybrid and BUS ( < 1 cm2 ) • Receiver, Glue Logic and memory under design  Xilinx Virtex family will still be used for prototyping (> 300 user I/O pins, RAM) • First prototype of CMOS SRAM rad-tolerant memory received (~ 0.5 MB) and under test • ASICs for logic: no activity yet • Serializer: plan to use two IC called “LOC1” developed in SOS by SMU Dallas (2.5 Gbps) • a LOC2 at 5 Gbps available by the end of 2009 • Laser drivers: commercial (Texas and Micrel) devices and GBT-LD under investigation • Duplex LC package for housing two VCSEL and fibers (tight but not impossible) Hybrid Design (optical solution) To DAQ EDRO EPMC EPMC Optical Fiber 60/80 MHz

17. Elements on the hybrid: • Share receiving, glue logic, memory and serializer of the “Optical link” solution • Ouput drivers: we are acquiring evaluation boards for three different drivers from MICREL • SY58600U (CML), SY58602U (400 mV LVPECL driver) operating up to 10.7 Gbps • SY58601U (800 mV LVPECL driver) operating up to 5 Gbps •  Based on the results we will propose a 2 or 4 copper lines solution Buffering Modulations Drivers Hp. All data out Hybrid Design (copper link) Cu bus < 20 Gbit/s Optical link 2.5 Gbit/s Edro like ROM Off detector low rad area Counting room On detector High rad area