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DBBC Project

DBBC Project. G. Tuccari, S. Buttaccio, G. Nicotra - Istituto di Radioastronomia CNR, Sezione di Noto - Italy M. Wunderlich - Max Planck Institute fuer Radioastronomie, Bonn - Germany Y. Xiang - Shanghai Astronomical Observatory, CAS – China

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DBBC Project

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  1. DBBC Project G. Tuccari, S. Buttaccio, G. Nicotra - Istituto di Radioastronomia CNR, Sezione di Noto - Italy M. Wunderlich - Max Planck Institute fuer Radioastronomie, Bonn - Germany Y. Xiang - Shanghai Astronomical Observatory, CAS – China G. Balodis - Faculty of Electronics and Telecommunications, University of Riga - Latvia DBBC - EVN CDR Meeting, Bologna May 2005

  2. DBBC Project overview • The main goal is to replace the existing terminal with a complete compact system to be used with any VSI compliant recorder or data transport • Hardware programmability is the main feature in order to optimize the architecture to the needed performance having the possibility to arrange different architecture in the same hardware support • Maximum Input and Output data rates are the limitation and are set so to satisfy the present and near future necessities • The new development is compatible with the existing terminals and correlators DBBC - EVN CDR Meeting, Bologna May 2005

  3. DBBC Project overview (cont.) • The new set of BBCs is fully up-gradable and ready to process in a future larger bandwidth with modified correlators • Upgrade or improvements will be mostly only software • Upgrade is also possible in hardware replacing compatible ‘pin-to-pin’ processing modules • Data out as VSI interface and modified MK4 formatter DBBC - EVN CDR Meeting, Bologna May 2005

  4. DBBCGeneral Features • Four IF Input in the range 1-512 , 512-1024, 1024-1536, 1536-2048 MHz • Four polarizations or bands available for a single group of output data channel selection • 230=1.073.741.824 Hz frequency sampling clock • Channel bandwidth ranging between 250KHz to 32 MHz • Tuning step 1 Hz or less if required • Station based fringe counter-rotation possible • Multiple architecture using fully re-configurable FPGA Core Modules • Modular realization for cascaded processing DBBC - EVN CDR Meeting, Bologna May 2005

  5. DBBC General Schematic View IFn (MHz) 1~512, 512~1024, 1024~1536, 1536~2048 IF 1 IF 2 IF 3 IF 4 AGC/ Filter AGC/ Filter AGC/ Filter AGC/ Filter A/D 1 A/D 2 A/D 1 A/D 2 HSI HSIR HSI HSIR HSI HSIR MK4/VSI max 64 ch CORE CORE CORE H-Maser 1074 MHz Synthesizer Distributor HSO HSOR HSO HSOR HSO HSOR Collector FS PC cPCI Linux PC cPCI Interfaces D/A Monitor DBBC - EVN CDR Meeting, Bologna May 2005

  6. Schematic Top View6U x 84 TE x 360 mm 10 MHz 1 PPS IF1 IF3 IF4 IF2 1 PPS 1.5V Vcore 1.5V Vcore 3.3V Dig 3.3V An 5V 12V 3.3V VAux Fs/2 D I S K Fs/4 Fs IF1 IF2 IF3 IF4 MK4 Ethernet VSI JTAG Analog CoreModule min 1 – max 16 (8 for a VLBA equivalent system) A/D min 1- max 4 (4 for a VLBA equivalent system) cPCI Linux PC and Interfaces FiLa FiLa DBBC - EVN CDR Meeting, Bologna May 2005

  7. System Components • Analog to digital converter ‘environment’ • 1074 MHz Synthesizer (commercial) • CoreModule boards • FPGAs Core Firmware Configurations • DA monitor • FiLa board (data insertion and collector) • VSI interface • PCI interfaces (commercial) • Linux PC Board (commercial) • System Management Software + Field System Integration DBBC - EVN CDR Meeting, Bologna May 2005

  8. Analog to digital converter ‘environment’ • Conversion Clock Fs=1.073.741.824 Hz or Fs/2, Fs/4, Fs/8 • MAX108 AD converter (under evaluation ATMEL AT84AS003) • Front-end power level control • Bandwidth 1-512 / 512-1024 / 1024-1536 / 1536-2048 MHz selection/filtering • Total power measurement • LVPECL differential data bus (ATMEL: LVDS) DBBC - EVN CDR Meeting, Bologna May 2005

  9. A/D Board Schematic View Total Power Power Level Control AD CONVERTER RX IF Anti-image Analog Filter 2X8bit Data LVPECL differential Band Reduction 1074 MHz Synthesizer H-Maser Interface 1PPS DBBC - EVN CDR Meeting, Bologna May 2005

  10. AD Board Layout DBBC - EVN CDR Meeting, Bologna May 2005

  11. DBBC CoreModule • A single module able to process more channels • More modules can be arranged in cascade • External buses: HIS/HSIR, HSO/HSOR, CCM/CCMR • HSI Input data bus, is propagated with HSIR • HSO Output data bus, is shared for multiple IF access • CCM/R Control/Configuration/Monitor bus DBBC - EVN CDR Meeting, Bologna May 2005

  12. DBBC Core Modules Cascade Architecture Stream IF 1-2-3-4 HSI | HSIR HSI | HSIR HSI | HSIR HSI | HSIR CORE CORE CORE CORE To Collector and VSI interface HSOR HSOR HSOR HSO HSOR HSO HSO HSO DBBC - EVN CDR Meeting, Bologna May 2005

  13. DBBC CORE Module Features • Different configuration can be supported: • SSB down converter • Wide band parallel FIR • Polyphase FIR + FFT • A module able to handle: • Maximum Input bandwidth 8.192 Gbit/s • Maximum Output bandwidth 4.096 Gbit/s • Control/Configuration bus through a common PCI interface DBBC - EVN CDR Meeting, Bologna May 2005

  14. Core Module Board • HIS/HSIR Cascade-able Input Bus 4x2x8bit @512 MHz equivalent • HSO Shared Output bus 2x32bit @32, 64MHz • CCM Control / Configuration bus 32bit • CCM Monitor bus to DA converter 12 bit @32,64 MHz • 1 FPGA VirII-1152pin, 3000 - 4000 - 6000 – 8000 • (to be evaluated Xilinx V4 device) • ‘Sandwich’ cascade method DBBC - EVN CDR Meeting, Bologna May 2005

  15. CoreModule Layout DBBC - EVN CDR Meeting, Bologna May 2005

  16. Digital Down Converter Configuration • SSB conversion between high data rate sampled IF band and lower data rate base band • LO as a Numerically Controlled Oscillator • Mixer as Complex as Look Up Table multiplier • Low-pass band filter Finite Impulse Response (FIR) filters cascade • Decimation because of the high ratio between IF and output data rate performed with CIC or multirate/multistage FIR • Bandwidth: 16, 8, 4, 2, 1, 0.5, 0.25 MHz DBBC - EVN CDR Meeting, Bologna May 2005

  17. Linux PC Board: System Management Software • Standard commercial PC board including HD • Configuration files for each FPGA stored on HD • Software interface for FPGA configuration • Software interface for servicing FPGAs (I/O registers access) • Software interface for A/D level control DBBC - EVN CDR Meeting, Bologna May 2005

  18. Software Management Structure Field System PC Ethernet cPCI PC + INT AD HD AD FPGA Module FPGA Module FPGA Module DBBC - EVN CDR Meeting, Bologna May 2005

  19. DBBC Prototype Status at April 2005 • AD Environment: - Conditioning modules developed (IRA) - AD Board developed, to be realized (MPI) • CoreModule: - Board developed, to be realized (IRA) - FPGA firmware configurations (IRA+SHAO): • 0.5, 1, 2, 4 MHz bwd, completed, • 0.25, 8, 16 MHz bwd, near to completion, to be tested • 0.125, 0.0625, 0.03125, 32 MHz ready in simulation • tunable base band with 1 Hz resolution • tuning range in Nyquist blocks of 64 and 128 MHz ready • tuning range in Nyquist blocks of 256, 512 MHz ready in simulation, under development DBBC - EVN CDR Meeting, Bologna May 2005

  20. DBBC Prototype Status at April 2005 (cont) • Insertion/Collector board: developed, to be realized (IRA) • Monitor: to be realized (IRA) • Synthesizer: commercial + ad hoc: developed, to be realized • 1.5V high current power supply ready (IRA) • cPCI under Linux PC: commercial • cPCI interfaces: commercial • Communication software: partially done (SHAO) DBBC - EVN CDR Meeting, Bologna May 2005

  21. DBBC Prototype Performance (Apr 2005) • Preliminary testing has been done in laboratory for the developed configurations • Good performance in conversion and tuning have been measured from 0 up to 2.5 GHz • Today with appropriate Nyquist zone pre-selection, L and S band can be directly down-converted and recorded with modified MK4 formatter (Noto and Seshan) • Testing with real observation started with mDBBC (IRA-SHAO agreement): fringes detected in analog-digital and digital-digital baselines. DBBC - EVN CDR Meeting, Bologna May 2005

  22. First Results with the mDBBC prototype(collaboration Italy-China) • First digital x analog fringes detected on Nov 23, 2004 in the Seshan-Urumuqi baseline • First digital x digital fringes detected on Feb 2, 2005 in the Noto-Seshan baseline DBBC - EVN CDR Meeting, Bologna May 2005

  23. Conclusions • The DBBC system is an high flexible instrument because is able to produce independent tunable channels for a full compatibility with the existing acquisition system and correlators. One CoreModule board is replacing a BBC module. • The DBBC system is able to handle polyphase + FFT architectures for producing contiguous not tunable channels. One CoreModule board is able to produce multiple channels. • Both solutions are possible within the same system adopting a variable number of AD and CoreModule units DBBC - EVN CDR Meeting, Bologna May 2005

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