A Fast, Analytical Estimator for the SEU-induced Pulse Width in Combinational Designs

1. A Fast, Analytical Estimator for the SEU-induced Pulse Width in Combinational Designs By: Rajesh Garg Charu Nagpal Sunil P. Khatri Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX

2. Outline • Introduction • Previous Work • Objective • Approach • Classification of Radiation Particle Strikes • Our Model • Experimental Results • Conclusions

3. Introduction • Modern VLSI Designs • Vulnerable to noise effects- crosstalk, SEU, etc • Single Event Upsets (SEUs) or Soft Errors • Troublesome for both memories and combinational logic • Becoming increasingly problematic even for terrestrial designs • Applications demand reliable systems • Need to efficiently design radiation tolerant circuits • Analyze circuits early in design flow • Hence need SEU robustness metric • Harden the circuits using these metrics • Approach depends on level of protection required • Need to satisfy delay, area and power constraints

4. SEU Robustness Metrics • SPICE based simulation of SEU events • Most accurate metric possible • Computationally expensive • Too many scenarios required to be simulated • Amount of charge dumped • State of circuit inputs • Need to simulate all nodes in a circuit • Hence we need an efficient and accurate SEU robustness metric • This is the focus of this talk

5. SEU Robustness Metrics • Accurate and efficient models for SEU events • Can be used to harden a circuit • Requires solving of non-linear differential equations. • Our metric is based on the pulse width of voltage glitch due to a radiation strike • Good measure of SEU robustness • Based on the pulse width, we can upsize susceptible gates • Easily incorporated in design flow

6. Radiation Particle Strike • Effects of radiation particle strike • Neutron, proton and heavy cosmic ions • Ions strike diffusion regions • Deposit charge • Results in a voltage spike • Radiation particle strike is modeled by a current pulse as where: Q is the amount of charge deposited ta is the collection time constant tb is the ion track establishment constant

7. Previous Work • Device-level simulation: Dodd et. al 1994, etc • Accurate but very time consuming • Not practical for circuit hardening • Logic-level simulation: Cha et. al 1996 • Abstract transient faults by logic-level models • Gate-level timing simulators are used • Highly inaccurate as a robustness metric for hardening purposes • Circuit-level simulation: • Intermediate between device and logic level simulation

8. Previous Work • Shih et. al 1992 solve transistor non-linear differential equation using infinite power series • Computationally expensive • Dahlgren et. al 1995 presented switch level simulator • Electrical simulations are performed to obtain the pulse width of a voltage glitch, using the R and C values of a gate • Pulse width for other R and C values are obtained using linear relationship between the obtained pulse width and the new R and C values • Cannot be used for different values of Q • Mohanram 2005 reports a closed form model for SEU induced transient simulation for combinational circuits • Linear RC gate model is used • Ignores the contribution of tb in iseu(t) – we find that this results in 10% error • Results in lower accuracy

9. Objective • Develop an analytical model for SEU induced transients in combinational circuits • Closed form analytical expression for the pulse width of voltage glitch • Accurate and efficient • Applicable to • Any logic gate • Different gate sizes • Different gate loading • Incorporates the contribution of tb time constant • Can be easily integrated in a design flow

10. Our Approach • Radiation particle strike at the output of INV1 • Implemented using 65nm PTM with VDD=1V • Radiation strike: Q=150fC, ta=150ps & tb=50ps M1 in Saturation M2 in Saturation M2’s Drain-Bulk diode is ON M1 in Saturation M2 in Saturation Models Radiation Particle Strike M1 in Saturation M2 in Cutoff M1 in Linear M2 in Cutoff M1 and M2 operate in different regions during radiation-induced transients Our approach estimates the pulse width of the transient by modeling these regions INV1 cannot be modeled accurately by a linear RC model (as was done in several previous approaches)

11. Classification of Radiation Strike • INV1 can operate in 4 different cases depending upon voltage glitch magnitude VGM (=Va) • Case 1: VGM ≥ VDD + 0.6V • Case 2: VDD+|VTP| ≤VGM < VDD + 0.6V • Case 3: 0.5*VDD ≤VGM <VDD+|VTP| • Case 4: VGM < 0.5*VDD Different analytical models are applicable to different cases to compute pulse width of the voltage glitch

12. Model Overview Given a gate G, its input state, the gates in the fanout of G and Q, ta and tb Cell library data IDS(VDS) forVGS=1 and 0, CG and CD Determine the value of VGM & case of operation If Case==4 Yes No Pulse Width is 0 Compute t1 If Case==1 use its model to compute t2 If Case==2 use its model to compute t2 If Case==3 use its model to compute t2 Compute Pulse Width as t2-t1

13. Voltage Glitch Magnitude (VGM) • IDS of NMOS transistor with gate terminal at VDD • Differential equation for radiation induced voltage transient at output of INV1 (1) Green Known Red  Unknown Va(t) VGM Integrate Equation 1 from (0, 0) to (Vdsat, Tsat) with Again integrate Equation 1 with initial condition (Vdsat, Tsat) and with Now VGM = Va(TVGM) Vdsat Obtain TVGM by differentiating Va(t) and solving dVa(t)/dt = 0 Solve for Tsat Tsat TVGM t * Details can be found in the paper

14. Voltage Glitch Magnitude (VGM) • VGM = Va(TVGM) where • X’, Y’ and Z’ are constants defined in the paper • is the time when iseu(t) is at its maximum value • Diff. eq. for radiation induced voltage transient at output of INV1 • Does not include the drain to source current of M2 (PMOS) • Accurate for Case 3 and 4 • In some cases, Case 2 VGM value can be diagnosed as Case 1- Pessimistic

15. Next Steps • Once we know VGM , we know which case is applicable (among cases 1, 2, and 3). • The magnitude of the SET induced glitch is t2 – t1 • Next, we find an expression for t1 (common for all 3 cases) • Then we will find expressions for t2 (separately for each of the 3 cases) • Note that case 4 is not of interest since the glitch magnitude is less than VDD/2 in case 4. • Lets do this over the next few slides…

16. Expression for t1 • If VGM > 0.5*VDD then there is a glitch Green Known Red  Unknown Va(t) VGM To obtain t1 , substitute Va(t1) = 0.5*VDD and solve for t1 using initial guess 0.5*VDD Vdsat Tsat t1 TVGM t

17. Expression for t2 : Case 1 • For Case 1, VGM ≥ VDD+0.6V • Va(t3) = VDD +|VTP| • IDS of PMOS M2 is zero • iseu (t3) = IDSof M1 • Also ignore tb • This gives us t3 below • Use, Va(t) = VDD +|VTP| at t = t3 as initial condition for integration. t3 VDD+|VTP|

18. Expression for t2 : Case 1 Va(t) iseu(t) • Approximate iseu(t) by a straight line Va(t) Green Known Red  Unknown Integrate Equation 1 with initial condition (VDD+|VTP|, t3) VGM VDD+|VTP| Substitute Va(t) = 0.5*VDD for t = t2 and solve for t2 by performing a quadratic expansion around initial guess 0.5*VDD t1 t3 t2 t* t • P, Q, R and t* are constants defined in the paper • Details of derivation of t2 can be found in the paper

19. Expression for t2 : Case 2 • For Case 2: VDD+|VTP|≤VGM<VDD+0.6V • Again use initial condition,Va(t)=VDD+|VTP| at t = t3 Va(t) Green Known Red  Unknown VGM VDD+|VTP| 0.5*VDD Integrate Equation 1 with initial condition (VDD+|VTP|, t3) To obtain t2 , substitute Va(t2)=0.5*VDD and solve for t2 by using initial guess t1 t2 t3 TVGM t

20. Expression for t2 : Case 3 • For Case 3: 0.5*VDD≤VGM<VDD+|VTP| Green Known Red  Unknown Va(t) VGM To obtain t2 , substitute Va(t2)=0.5*VDD and solve for t2 by using initial guess 0.5*VDD Vdsat Tsat t1 t2 TVGM t

21. Experimental Results • Implemented our model in Perl • Library of INV, NAND and NOR gates • Using 65nm PTM model card with VDD=1V • Characterized each gate for IDS, CG and CD • Applied our model to INV and NAND2 • For different values of Q, ta and tb • Different gate sizes and loads • Our model is 1000X faster compared to SPICE

22. Experimental Results • Radiation particle strike at the output INV1 with Q=150fC, ta=150ps and tb = 50ps

23. Experimental Results • NAND2 gate with Q=150fC, ta=150ps and tb = 50ps • Average pulse width estimation error compared to SPICE

24. Conclusion • A SEU robustness metric is required to design radiation tolerant circuits efficiently • We presented an analytical model to compute this metric (which is the pulse width of the SEU induced glitch) • Pulse width of the glitch is a good measure of SEU robustness • Our model is accurate and efficient • Pulse width estimation error is 3% compared to SPICE • Our method is 1000X faster than SPICE • Our model gains accuracy • By using the transistor current model (and avoiding a linear RC model for the gate) • By including the contribution of tb • Our model can be easily incorporated in a design flow to test robustness. Based on the results, hardening can be performed.

25. Thank You

26. BACKUP SLIDES

27. Voltage Glitch Magnitude (VGM) • IDS of NMOS transistor with gate terminal at VDD • For 65nm PTM model card Vdsat< 0.5*VDD • Integrate Eq. 1 from Va(t)=0 at t=0 to Va(t)=Vdsat at t=Tsatusing IDS = Va/RDS • Solve for Tsat by linearly expanding around initial guess Tasat, we get

28. Voltage Glitch Magnitude (VGM) • To calculate Tasat, approximate the rising part of iseu(t) by a line • Substitute iseu(t) in Eq. 1 by a line between origin and Imaxseu • Integrate Eq. 1 from Va(t)=0 at t=0 to Va(t)=Vdsat at t=Tasat • Solve for Tasatby quadratic expansion around origin • Now, integrate Eq. 1 with initial condition Va(t)=Vdsat at t=Tsat • Use IDS = K3 + K4.VDSfor this integration (2)

29. Voltage Glitch Magnitude (VGM) • Differentiate Va(t) (Eq. 2) and solve dVa(t)/dt =0 forTVGM • Linearly expand around Tmaxseu • Now, VGM = Va(TVGM) • If VGM > VDD + 0.6V then set VGM = VDD + 0.6V • Diode is not modeled in Eq. 2

30. Expression for t1 • If VGM > 0.5*VDD then there is a glitch • Substitute t = t1 and Va(t1) = 0.5*VDD in Eq. 2 • Expand linearly around ta1 = TsatVDD/(2Vdsat) (3) • Eq. 3 is used to compute t1 for Cases 1, 2 and 3

31. Expression for t2 : Case 1 • For Case 1, VGM ≥ VDD+0.6V • Va(t3) = VDD-|VTP| • IDS of PMOS M2 is zero • iseu (t3) = IDSof M1 • Use, Va(t) = VDD-|VTP| at t = t3 as initial condition • To calculate t3, ignore tb in iseu(t) • ta is 3-4 times larger than tb • e-t/tb around t3 will be close to 0 t3 VDD-|VTP|

32. Expression for t2 : Case 1 • Model iseu(t) by a straight line for t >t3 between (IDSavg,t3) and (0, t*) • TBD what is ids avg • Obtain t* by equating charge deposited by iseu(t) and the above straight line model for t >t3 • Integrate INV1 output node diff. equation (Eq. 1) • Initial condition: Va(t) = VDD-|VTP| for t = t3 • Substitute Va(t) = 0.5*VDD for t = t2 and solve for t2 • t2a1 is the initial guess for t2 • Integrate Eq. 1 with IDSVa = IDSVDD+|VTP| and line mode for iseu(t) • Substitute Va(t) = 0.5*VDD for t = t2a1 and solve for t2a1 • Closed form exp. of t2a1 is

33. Expression for t2 : Case 2 • In this case also, Va(t3) = VDD-|VTP| • Integrate INV1 output node diff. equation (Eq. 1) • Initial condition: Va(t) = VDD-|VTP| for t = t3 • Use original expressions for iseu(t) and IDSVa • Substitute Va(t) = 0.5*VDD for t = t2 • Expand around initial guess t2a2for t2 and solve for t2 • Calculate t2a2by solving equation iseu(t2a2)= IDSVDD/2 • t2a2 > Tseumax (Time when iseu(t) reaches its maximum value) • Ignore e-t/tb term iniseu(t)

34. Expression for t2 : Case 3 • In this case, only M1 conducts • Substitute Va(t) = 0.5*VDD for t = t2 in Eq. 2 • Va(t) equation as shown before • Solve for t2 after expanding around initial guess t2a2for t2 where • Now we can calculate the pulse width as t2 - t1