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Lecture 5. AT91 Timers and AIC

COMP427 Embedded Systems. Lecture 5. AT91 Timers and AIC. Prof. Taeweon Suh Computer Science Education Korea University. Timers in AT91. There are 3 counter channels in AT91. Base Address: 0xFFFE_0000. clock. 16-bit counter (incrementing). ?. Register A (RA) (0x14). ?.

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Lecture 5. AT91 Timers and AIC

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  1. COMP427 Embedded Systems Lecture 5. AT91 Timers and AIC Prof. Taeweon Suh Computer Science Education Korea University

  2. Timers in AT91 • There are 3 counter channels in AT91 Base Address: 0xFFFE_0000 clock 16-bit counter (incrementing) ? Register A (RA) (0x14) ? Register B (RB) (0x18) Reset 1. SWTRG: TC_CCR (0x00) 2. SYNC: external signal 3. RC: if RC == counter value ? Register C (RC) (0x1C) Counter Value (0x10) Status Register (0x20) Interrupt Enable Register (0x24) • Status Register: RA, RB, RC compare status etc

  3. Capture Mode in Timers TIOA which edge of TIOA (LDRA in TC_CMR) clock 16-bit counter (incrementing) Register A (RA) (0x14) ? which edge of TIOA (LDRB in TC_CMR) Register B (RB) (0x18) ? reset ? Register C (RC) (0x1C) WAVE = 0 in TC_CMR (0x04) Counter Value (0x10) Status Register (0x20) Interrupt Enable Register (0x24) RC compare Interrupt

  4. Waveform Mode in Timers TIOA clock 16-bit counter (incrementing) Register A (RA) (0x14) ? TIOB Register B (RB) (0x18) Waveform (PWM: Pulse Width Modulation) reset ? ? Register C (RC) (0x1C) WAVE = 1 in TC_CMR (0x04) Counter Value (0x10) Status Register (0x20) Interrupt Enable Register (0x24) RA, RB RC compare Interrupts

  5. AIC (Advanced Interrupt Controller) Base Address: 0xFFFF_F000 Set Priority US0_IRQ nIRQ SMR 0 (0x000) Source Vector Register 0 (0x080) nFIQ US1_IRQ SMR 1 (0x004) Source Vector Register 1 (0x084) TC0_IRQ SMR 2 (0x008) Source Vector Register 2 (0x088) TC1_IRQ IRQ Vector Reg (0x100) ….. ….. TC2_IRQ FIQ Vector Reg (0x104) SMR 29 (0x074) Source Vector Register 29 (0x0F0) IRQ0_IRQ SMR 30 (0x078) Source Vector Register 30 (0x0F8) IRQ1_IRQ SMR 31 (0x07C) Source Vector Register 31 (0x0FC) IRQ2_IRQ Interrupt Enable Reg (0x120) End of Interrupt Reg (0x130)

  6. Edge or Level-triggered Interrupt Timer AIC

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