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Combined voltage space vector locations of a dual five-level inverter fed open-end winding IM drive (a nine-level inverter). 217 Combined Voltage Vectors Triangular Sectors 15,625 Switching State Combinations. Shaded voltage vectors generate zero common-mode

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slide1

Combined voltage space vector locations of a dual five-level inverter fed open-end winding IM drive (a nine-level inverter)

  • 217 Combined Voltage
  • Vectors
  • Triangular Sectors
  • 15,625 Switching State
  • Combinations
  • Shaded voltage
  • vectors generate
  • zero common-mode
  • voltage

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide2

Common-mode voltage of the dual five-level inverter fed open-end winding IM drive

  • Common-mode voltage generated by individual five-level inverters
  • (Inverter-A or Inverter-A’)

Inverter-A

Inverter-A’

  • Common-mode voltage in the phase voltage of induction motor with
  • the proposed dual five-level inverter fed drive

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide3

Groups of common-mode voltage generated by individual five-level inverter

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide4

Voltage vectors and corresponding switching states resulting into zero common-mode voltage in individual five-level inverter (Inv.-A or Inv.-A’)

19 Voltage Vectors

24 Triangular Sectors

19 Switching States

  • All the shaded switching
  • states belong to the
  • Group-7,which generate
  • zero common-mode
  • voltage at the inverter
  • poles
slide5

Combined voltage space phasor locations resulting into zero common-mode voltage (a five-level inverter voltage space phasor structure)

61 Combined Voltage

Vectors

96 Triangular Sectors

361 Switching State

Combinations

  • Achieved when individual
  • five-level inverters (Inv.-A
  • and Inv.-A’) are switched
  • using the switching states
  • belonging to the Group-7
  • only.
slide6

Number of redundant switching states available for each voltage vectors of the five-level inverter with zero common-mode voltage

61 Combined Voltage

Vectors

96 Triangular Sectors

361 Switching Stats

Combinations

  • Achieved when individual
  • five-level inverters (Inv.-A
  • and Inv.-A’) are switched
  • using the switching states
  • belonging to the Group-7
  • only.
slide7

Some of the voltage vectors and their redundant switching states for five-level inverter with zero common-mode voltage

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide8

Amplitude of maximum reference space vector possible in linear range of modulation without boost in the DC-link of the proposed inverter

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide9

Generation of same maximum peak fundamental amplitude of the phase voltage equivalent to that of a conventional SVPWM

based five-level inverter

  • A boost of 15% in the dc-link of the proposed drive is
  • required to generate the maximum peak fundamental
  • amplitude of the phase voltage equivalent to that of a
  • conventional SVPWM based five-level inverter.

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide10

Voltage space vector locations for proposed five-level inverter with common-mode voltage elimination (with dc-link boost)

61 Combined Voltage

Vectors

96 Triangular Sectors

361 Switching Stats

Combinations

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide11

Switching state combination selected to generate the voltage space phasors of five-level inverter with zero CMV

61 Combined Voltage

Vectors

96 Triangular Sectors

61 Switching Stats

Combinations

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide12

Power scheme of the proposed five-level inverter with CME

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide13

Experimental results

Pole voltage (VAO)

Two-level operation

Y-axis: 1 div. = 50 V

X-axis: 1 div. = 10 ms

Phase voltage (VA’A)

Pole voltage (VA’O)

Phase voltage FFT

(two-level operation)

Y-axis: Normalized amplitude

X-axis: Order of harmonic

Pole voltage FFT

(two-level operation)

Y-axis: Normalized amplitude

X-axis: Order of harmonic

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide14

Experimental results (contd…)

Pole voltage (VAO)

Three-level operation

Y-axis: 1 div. = 40 V

X-axis: 1 div. = 10 ms

Phase voltage (VA’A)

Pole voltage (VA’O)

Phase voltage FFT

(three-level operation)

Y-axis: Normalized amplitude

X-axis: Order of harmonic

Pole voltage FFT

(three-level operation)

Y-axis: Normalized amplitude

X-axis: Order of harmonic

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide15

Experimental results (contd…)

Pole voltage (VAO)

Four-level operation

Y-axis: 1 div. = 70 V

X-axis: 1 div. = 5 ms

Phase voltage (VA’A)

Pole voltage (VA’O)

Phase voltage FFT

(four-level operation)

Y-axis: Normalized amplitude

X-axis: Order of harmonic

Pole voltage FFT

(four-level operation)

Y-axis: Normalized amplitude

X-axis: Order of harmonic

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide16

Experimental results (contd…)

Pole voltage (VAO)

Five-level operation

Y-axis: 1 div. = 75 V

X-axis: 1 div. = 5 ms

Phase voltage (VA’A)

Pole voltage (VA’O)

Phase voltage FFT

(five-level operation)

Y-axis: Normalized amplitude

X-axis: Order of harmonic

Pole voltage FFT

(five-level operation)

Y-axis: Normalized amplitude

X-axis: Order of harmonic

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide17

Experimental results (contd…)

Pole voltage (VAO)

Over-modulation operation

Y-axis: 1 div. = 80 V

X-axis: 1 div. = 5 ms

Phase voltage (VA’A)

Pole voltage (VA’O)

Phase voltage FFT

(over-modulation operation)

Y-axis: Normalized amplitude

X-axis: Order of harmonic

Pole voltage FFT

(over-modulation operation)

Y-axis: Normalized amplitude

X-axis: Order of harmonic

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide18

Experimental results (contd…)

Phase voltage (VA’A)

Y-axis: 1 div. = 50 V

Four-level operation

X-axis: 1 div. = 5 ms

Phase current

Y-axis: 1 div. = 1 A

Phase voltage (VA’A)

Y-axis: 1 div. = 50 V

Five-level operation

X-axis: 1 div. = 5 ms

Phase current

Y-axis: 1 div. = 1 A

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide19

Salient features of the proposed common-mode elimination scheme for multilevel inverter fed drive

  • A dual five-level inverter fed open-end winding induction motor
  • drive with elimination of common-mode voltage in the entire
  • operating range.
  • Each five-level inverter of the proposed drive is formed by
  • cascading two conventional two-level inverters and a conventional
  • three-level NPC inverter. Hence, the proposed drive offers simple
  • power-bus structure compared to the five-level NPC inverter fed
  • drive.
  • There is no alternating common-mode voltage in the inverter
  • poles as well as at the phase windings of the induction machine.

CEDT, Indian Institute of Science CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide20

Salient features of proposed common-mode elimination scheme for multilevel inverter fed drive (contd…)

  • A common DC-link is used at both the ends of the open-end
  • winding induction machine, for both the five-level inverters.
  • The DC-link voltage requirement of proposed open-end winding
  • IM drive is nearly half as compared to that of a single five-level
  • inverter fed conventional IM drive.
  • Hence, the voltage stress on the devices is reduced and devices
  • with lower voltage blocking capability can be used, which makes
  • the proposed drive scheme suitable for high power applications.

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

conclusion
In the implemented scheme, the rotor flux position is estimated from the motor phase current ripples

During the low speed region of operation, the current ripple during the zero vector periods are used for rotor flux position estimation

During the high speed region of operation, the current ripple during the active vector periods are used for rotor flux position estimation

The scheme is implemented for a three phase motor, but the scheme can be extended to any multi phase motor and also with open-end winding structure

CONCLUSION

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide22

Linearization of the Multi-level SVPWM in Over-modulation Region

By

R. S. Kanchan, P. N. Tekwani, and K. Gopakumar

Centre for Electronic Design and Technology,

Indian Institute of Science

Bangalore, INDIA

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide23

v

v

v

AN

BN

CN

0.5

Reference signals

Vt

and carrier

V

/2

dc

-0.5

a0

V

-V

/2

dc

V

/2

dc

b0

V

-V

/2

dc

V

/2

dc

c0

2 π

3 π/2

(wt)

π/2

π

V

-V

/2

dc

Linearization of the Multi-level SVPWM in the Over-Modulation Region

Conventional two-level Sine-Triangle PWM

The fundamental component in the output PWM waveform is equal to

k = (peak amplitude of the sinusoidal reference) / (height of the triangular carrier signal)

  • Three sinusoidal (1200 phase shifted) reference signals are compared with triangular carrier
  • The PWM signals are generated for three phases
  • The pole voltage is clamped to +ve DC link bus if Vref >Vt else to –ve DC link bus

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide24

V

V

V

CN

AN

BN

V

/2

dc

-V

/2

dc

V

/2

dc

a0

V

-V

/2

dc

V

/2

dc

b0

V

-V

/2

dc

V

/2

dc

c0

V

-V

/2

dc

(wt)

3 π/2

π

2 π

π/2

Linearization of the Multi-level SVPWM in the Over-Modulation Region

Conventional Sine-Triangle PWM: Over-Modulation Range

  • When ref signal is greater than carrier, the pole voltages are clamped to the DC link bus voltage
  • The fundamental component in output PWM waveform is not given by
  • But there is reduction in the fundamental component in the output voltage

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide25

0.5

0

π/2

π

00

wt

Linearization of the Multi-level SVPWM in the Over-Modulation Region

Conventional Sine-Triangle PWM: Over-Modulation Range

  • Reduction in the output fundamental is proportional to the shaded area

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide26

0.637

0.50

Non-linear characteristic

k

Linear range

Over-modulation

0.7854

MI

Linearization of the Multi-level SVPWM in the Over-Modulation Region

Conventional Sine-Triangle PWM

  • The voltage transfer characteristics i.e the ratio between the output fundamental and the reference signal amplitude is non-linear in the over-modulation region

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide27

v*BN

v*CN

v*AN

0.5

and carrier

Reference signals

-0.5

200

400

600

800

1000

1200

1400

1600

1800

V

/2

dc

a0

V

-V

/2

dc

200

400

600

800

1000

1200

1400

1600

1800

V

/2

dc

b0

V

-V

/2

dc

200

400

600

800

1000

1200

1400

1600

1800

V

/2

1

dc

c0

V

-V

/2

dc

2 π

3 π/2

π/2

π

(wt)

Linearization of the Multi-level SVPWM in the Over-Modulation Region

Carrier based Space-Vector PWM (SVPWM)

  • The reference signals are added with an offset voffset1
  • The resultant PWM is a Space Vector PWM

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide28

0.5

0

π/2

00

wt

π/6

π/3

2π/3

π

Linearization of the Multi-level SVPWM in the Over-Modulation Region

Carrier based Space-Vector PWM (SVPWM)

  • Again when ref signal is greater than carrier, the pole voltages are clamped to the DC link bus voltage
  • There is reduction in the fundamental component in the output voltage
  • Reduction in the output fundamental is proportional to the shaded area

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide29

0.637

0.577

0.5

SPWM

SVPWM

Non-linear characteristic

Output voltage (per unit w.r.t Vdc )

0.866

Linear range

Over-modulation

0.785

MI

Linearization of the Multi-level SVPWM in the Over-Modulation Region

  • The extended linear region in SVPWM as compared to SPWM
  • The voltage transfer characteristics is again non-linear in the over-modulation region similar to SPWM

Ideal requirement for the PWM modulator : Linear voltage transfer characteristics

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide30

Linearization of the Multi-level SVPWM in the Over-Modulation Region

In the Proposed Work

  • An over-modulation scheme with the linear voltage transfer characteristics for a general n-level SVPWM signal generation
  • Reference signal to the PWM modulator is pre-scaled in over-modulation region such that
      • The fundamental component of the original and the modified reference signal is same
      • The modified reference signal is always within carrier region
  • Thus voltage transfer characteristic is a linear function of the modulation index both in the linear-modulation as well as in the over-modulation region
  • The inverter leg switching times are directly obtained with a simple algorithm using only the sampled amplitudes of the reference phase voltages

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide31

Linearization of the Multi-level SVPWM in the Over-Modulation Region

Principle of linearization: when k=0.637 i.e. six step mode

k=0.637

  • F1, the original reference signal in six step mode ( f1 (pk)=0.637) goes above the carrier (0.5)
  • The output voltage will be less, if f1 is used for PWM generation
  • f2 is a rectangular signal such that fundamental component of f2 is equal to f1, the original reference signal in six step mode i.e. F2 (1)=0.637
  • Therefore, f2 can be used for PWM generation instead of f1

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide32

0.5

0

signal

Reference

-0.5

1

1

f

0

-1

1

2

f

0

-1

0.5

signal

0

modified ref.

-0.5

3 π/2

2 π

π/2

π

θ

π-θ

2π-θ

π+θ

Linearization of the Multi-level SVPWM in the Over-Modulation Region

Principle of linearization: when 0.5 < k < 0.637

  • A part of original reference signal is clamped
  • The fundamental component of the modified reference signal is same as original reference signal
  • This requires that the fundamental component of rectangular pulse f2 is equal to fundamental component of part of the original reference signal f1

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide33

0.5

0

signal

Reference

-0.5

1

1

f

0

-1

1

2

f

0

-1

0.5

signal

modified ref.

0

-0.5

3 π/2

2 π

π/2

π

θ

π-θ

2π-θ

π+θ

Linearization of the Multi-level SVPWM in the Over-Modulation Region

  • Fundamental component of part of the original reference signal f1 =
  • Fundamental component of rectangular pulse f2 =

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide34

1

0.9739

0.9524

0.9111

MI

0.8796

0.8482

0.8168

0.7854

0

10

20

30

40

50

60

70

80

90

q

Linearization of the Multi-level SVPWM in the Over-Modulation Region

  • The relationship between modulation index MI and clamping angle q
  • Thus if MI is known, the clamping angle q can be determined
  • The modified reference signal is clamped for the angle q to π-θand π+θ to 2π-θ

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide35

0.5

0

00

π

π/3

π/2

π/6

2π/3

wt

Linearization of the Multi-level SVPWM in the Over-Modulation Region

Principle of the proposed SVPWM in the over-modulation region

  • Modified reference signal
  • Reference signal goes out of the carrier two times in the positive half cycle

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide36

0.5

θ0

(2π/3-θ)0

0

π/3

π

π/2

π/6

2π/3

wt

00

Linearization of the Multi-level SVPWM in the Over-Modulation Region

Principle of the proposed SVPWM in the over-modulation region

  • The reference signal is clamped to 0.5 twice in +ve half cycle
  • Again the fundamental component of the modified reference signal is same as original reference signal

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide37

Linearization of the Multi-level SVPWM in the Over-Modulation Region

Principle of the proposed SVPWM in the over-modulation

  • The fundamental component of the original reference signal f1 between q to 2π/3-θ

0.5

θ0

(2π/3-θ)0

  • The fundamental component of rectangular pulse f2 between q to 2π/3-θ

0

0.5

  • For the fundamental component of the modified reference signal to be same as original signal,

θ0

(2π/3-θ)0

0

π/3

π/2

wt

π/6

00

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide38

Linearization of the Multi-level SVPWM in the Over-Modulation Region

Principle of the proposed SVPWM in the over-modulation

  • The relationship between modulation index MI and clamping angle q
  • Thus if MI is known, the clamping angle θ can be determined
  • Clamping of the modulating signal starts when

0.5

and clamping angle θ is equal to π/3

  • When clamping angle = π/6, k =0.60337
  • Thus the clamping scheme can be used only in the range 0.577<k <0.60337 as the clamping starts at an angle less than π/6, where modulating wave is (3/2)ksin(wt) instead of

θ0

This is referred as over-modulation Mode-I (0.577<k <0.60337)

(2π/3-θ)0

0

π/3

π/2

π/6

wt

00

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide39

Linearization of the Multi-level SVPWM in the Over-Modulation Region

Principle of the proposed SVPWM in the over-modulation MODE-II

  • The reference signal is clamped to 0.5 for θ < wt < π- θ
  • Again the fundamental component of the modified reference signal is same as original reference signal (dotted line)
  • The MI range greater than 0.60337, angle θ at which clamping starts is less than π/3

.

0.5

θ0

(π-θ)0

0

π

π/3

π/2

π/6

2π/3

wt

00

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide40

.

0.5

θ0

(π-θ)0

0

wt

π/3

2π/3

5π/6

π

π/2

π/6

00

Linearization of the Multi-level SVPWM in the Over-Modulation Region

Principle of the proposed SVPWM in the over-modulation MODE-II

  • The relationship between θ and k can be derived similarly

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide41

Linearization of the Multi-level SVPWM in the Over-Modulation Region

Principle of the proposed SVPWM in the over-modulation MODE-II

Summary: The relationship between θ and k

  • Over-modulation Mode-I (0.577<k <0.60337) & clamping angle π/3<θ< π/6
  • Over-modulation Mode-II (0.60337<k <0.637) & clamping angle 0<θ< π/3

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide42

Mode-II

Mode-I

Linearization of the Multi-level SVPWM in the Over-Modulation Region

The relationship between θ and k (MI)for SPWM and SVPWM

  • Steps
  • Read Modulation Index MI
  • Determine clamping angle θ
  • Clamp the reference signal to 0.5 appropriately
  • The implementation needs instantaneous angle information

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide43

Space Vector PWM signal generation for multi-level inverters using only the sampled amplitudes of reference phase voltages

Modified reference voltages and triangular carriers for a five-level SVPWM scheme

  • n-level SPWM scheme uses n-1 level shifted carrier waves
  • Sinusoidal reference signals are added with offset which centers them within carrier region

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide44

Space Vector PWM signal generation for multi-level inverters using only the sampled amplitudes of reference phase voltages

Determination of the Ta_cross , Tb_cross and Tc_cross during switching interval TS (When reference voltages are spanning the inner carrier region, MI < 0.433)

Ta_cross , Tb_cross and Tc_cross : the time duration from the start of switching interval when the reference phase - A, B and C cross the carrier

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide45

Space Vector PWM signal generation for multi-level inverters using only the sampled amplitudes of reference phase voltages

Determination of the Ta_cross , Tb_cross and Tc_cross during switching interval TS (When reference voltages are spanning the inner carrier region, MI < 0.433)

Carrier- C1

Carrier- C2

Carrier- C2

T*as , T*bs and T*cs : Time equivalents of the modified reference signal amplitudes

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide46

Space Vector PWM signal generation for multi-level inverters using only the sampled amplitudes of reference phase voltages

Determination of the Ta_cross , Tb_cross and Tc_cross during switching interval TS (When reference voltages are spanning the entire carrier region, 0.433<MI < 0.866)

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide47

Space Vector PWM signal generation for multi-level inverters using only the sampled amplitudes of reference phase voltages

SUMMARY: Ta_cross , Tb_cross and Tc_cross for various carrier regions to bring the reference within a carrier region

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide48

Space Vector PWM signal generation for multi-level inverters using only the sampled amplitudes of reference phase voltages

3600

00

900

1800

2700

wt

Determination of the Ta_cross:

Represent the carriers and ref. signals in terms of time equivalents using relationship

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide49

Space Vector PWM signal generation for multi-level inverters using only the sampled amplitudes of reference phase voltages

3600

00

900

1800

2700

wt

Determination of the Ta_cross:

Shift the ref. signal into one carrier region (first +ve carrier) by adding proper offset

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide50

Space Vector PWM signal generation for multi-level inverters using only the sampled amplitudes of reference phase voltages

3600

00

900

1800

2700

wt

Determination of the Ta_cross

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide51

Space Vector PWM signal generation for multi-level inverters using only the sampled amplitudes of reference phase voltages

3600

00

900

1800

2700

wt

Determination of the Ta_cross

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide52

Space Vector PWM signal generation for multi-level inverters using only the sampled amplitudes of reference phase voltages

00

900

1800

00

900

1800

Equivalence to Conventional SVPWM

  • The reference signals in carrier based SVPWM are shifted to one carrier region
  • The outer sub-hexagon in the conventional SVPWM are shifted to central sub-hexagon in conventional SVPWM
  • The reference signal shifting in carrier based SVPWM is equivalent to sub-hexagonal shifting in the conventional SVPWM

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide53

Space Vector PWM signal generation for multi-level inverters using only the sampled amplitudes of reference phase voltages

Algorithm for inverter leg switching time calculation: Tfirst_cross , Tsecond_cross and Tthird_cross : the time duration from the start of switching interval when the reference phases cross the carrier for first, second and third time respectively.

, x= a, b, c

Inverter leg switching times

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide54

Space Vector PWM signal generation for multi-level inverters using only the sampled amplitudes of reference phase voltages

Tgfirst_cross , Tgsecond_cross and Tgthird_cross : the inverter leg switching time for the reference phases which cross the carrier for first, second and third time respectively.

The traces of Tgfirst_cross , Tgsecond_cross and Tgthird_cross showing centered time duration for middle vectors

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide55

Space Vector PWM signal generation for multi-level inverters using only the sampled amplitudes of reference phase voltages

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide56

Space Vector PWM signal generation for multi-level inverters using only the sampled amplitudes of reference phase voltages

Schematic representation of the Multi-level SVPWM

Inverter

Gating Signals

PWM

Compa-

rators

Gating

Signals

Tgx

Ta_cross,

Tb_cross

Tc_cross

VAN

Time

Equivalents

Txs

+

VBN

+

VCN

Toffset1

Toffset2

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide57

Implementation of the Multi-level SVPWM with Linear Transfer Characteristics in Over-Modulation

In overmodulation, clamps the reference signals appropriately

MI

Vs

Inverter

Gating Signals

PWM

Compa-

rators

Gating

Signals

Tgx

Ta_cross,

Tb_cross

Tc_cross

Pre-

scaler

VAN

+

Time

Equivalents

Txs

VBN

Toffset2

+

VCN

Toffset1

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide58

0.5

0.5

A

A

SVPWM MODE-II, (θ< π/6)

SVPWM MODE-I, (θ> π/6)

0

0

π

00

π/2

π

π/2

wt

wt

00

Implementation of the Multi-level SVPWM with Linear Transfer Characteristics in Over-Modulation

  • Pre-scaler:
  • Read Modulation Index MI
  • Determine clamping angle θand then Clamping level ‘A’
  • Clamp the reference signal if it is greater than ‘A’

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide59

0.5

60

50

0.4

40

0.3

A

Clamping level \'A\'

q

30

0.2

θ

20

0.1

10

0

0

0.9

0.92

0.94

0.96

0.98

1

Modulation Index \'MI\'

Linearization of the Multi-level SVPWM in the Over-Modulation Region

  • The clamping angle information is converted into a level signal ‘A’
  • Prescaler: A simple look-up table of MI vs A

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide60

MI

Vs

PWM

Compa-

rators

Gating

Signals

Tgx

Ta_cross,

Tb_cross

Tc_cross

Pre-

scaler

VAN

Time

Equivalents

Txs

+

VBN

Toffset2

+

VCN

Toffset1

Simulation Results: Linear-Modulation Region

  • No clamping of Tas in linear range of modulation
  • Pre-scaler is inactive in linear modulation range

(wt)

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide61

(wt)

Simulation Results: Over-Modulation Region (MI: 0.92)

  • Clamping of Tas in over-modulation (Mode-I)
  • Pre-scaler is active in over-modulation range

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide62

(wt)

Simulation Results: Over-Modulation Region (MI: 0.94)

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide63

(wt)

Simulation Results: Over-Modulation Region (MI: 0.95)

  • Clamping of Tas in over-modulation (Mode-II)
  • Pre-scaler is active in over-modulation range

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide64

(wt)

Simulation Results: Over-Modulation Region (MI: 0.96)

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide65

(wt)

Simulation Results: Over-Modulation Region (MI: 0.98 )

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide66

(wt)

Simulation Results: Over-Modulation Region (MI: 1.00)

  • Square-wave switching mode

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide67

Experimental verification: Five-level inverter fed IM drive configuration

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide68

+

Inv1

Inv2

-

Five-level inverter fed IM drive configuration

Inverter-A

  • Each three-level inverter configuration by cascading two two-level inverters
  • The pole voltage can attain three levels:Vdc/2, 0 ,
  • -Vdc/2

Ref: V. T. Somasekhar, K. Gopakumar, “Three - level inverter configuration cascading two 2-level inverters”, IEE Proc. – EPA, Vol. 150, No. 3, May 2003, pp.245-254

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide69

+

+

Inv3

Inv1

-

-

Inv4

+

Inv2

+

Induction

motor

-

-

Five-level inverter fed IM drive configuration

Ref: M. R. Baiju, K. K. Mohapatra, V. T. Somasekhar, K. Gopakumar and L. Umanand, “A five-level inverter voltage space phasor generation for an open-end winding induction motor drive”, IEE Proc. EPA, Vol. 150, No. 5, Sept 2003, pp: 531-538

  • Five-level space phasor generation across induction motor windings : Vdc/2,Vdc/4, 0 , -Vdc/4, or -Vdc/2

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide70

Experimental Results: The traces of pre-scaler output T*as and inverter leg switching time Tga

Linear-Modulation Region (MI: 0.906)

T*as

Tga

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide71

Experimental Results: The traces of pre-scaler output T*as and inverter leg switching time Tga

Over-Modulation Region (MI: 0.92)

T*as

Tga

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide72

Experimental Results: The traces of pre-scaler output T*as and inverter leg switching time Tga

Over-Modulation Region (MI: 0.94)

T*as

Tga

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide73

Experimental Results: The traces of pre-scaler output T*as and inverter leg switching time Tga

Over-Modulation Region (MI: 0.96)

T*as

Tga

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide74

Experimental Results: The traces of pre-scaler output T*as and inverter leg switching time Tga

Over-Modulation Region (MI: 0.98)

T*as

Tga

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide75

Experimental Results: The traces of pre-scaler output T*as and inverter leg switching time Tga

Square wave switching mode (MI: 1.00)

T*as

Tga

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide76

Experimental Results: The traces machine phase voltage and inverter leg switching time Tga

Linear modulation region (MI: 0.906)

Phase voltage

Tga

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide77

Experimental Results: The traces machine phase voltage and inverter leg switching time Tga

Over-Modulation Region (MI: 0.926)

Phase voltage

Tga

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide78

Experimental Results: The traces machine phase voltage and inverter leg switching time Tga

Over-Modulation Region (MI: 0.97)

Phase voltage

Tga

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide79

Experimental Results: The traces machine phase voltage and inverter leg switching time Tga

Square wave switching mode (MI: 1.00)

Phase voltage

Tga

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide80

Experimental Results: The traces machine phase voltage and phase current

Linear-Modulation Region (MI: 0.906)

Phase voltage

Phase current

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide81

Experimental Results: The traces machine phase voltage and phase current

Linear-Modulation Region (MI: 0.93)

Phase voltage

Phase current

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide82

Experimental Results: The traces machine phase voltage and phase current

Linear-Modulation Region (MI: 0.957)

Phase voltage

Phase current

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide83

Experimental Results: The traces machine phase voltage and phase current

Linear-Modulation Region (MI: 0.97)

Phase voltage

Phase current

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide84

Experimental Results: The traces machine phase voltage and phase current

Square wave switching mode (MI: 1.00)

Phase voltage

Phase current

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide85

Experimental Results: Transition from Linear to square wave switching mode

Top Trace: time equivalent of modified reference signalsT*as

Bottom Trace: Inverter gate switching time Tga

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide86

Experimental Results: Transition from Linear to six-step mode

Top Trace: Phase voltage, Bottom Trace: Phase current

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide87

1

0.9

0.8

0.7

0.6

(P.U.)

0.5

fund

V

0.4

0.3

0.2

0.1

0

0

10

20

30

40

50

60

70

80

90

100

MI (%)

Fundamental output voltage as a function of modulation index-MI

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide88

Harmonic components in the output waveform in the over-modulation region

0.25

5

7

11

0.2

13

0.15

Harmonic (P.U.)

0.1

th

n

0.05

0

90

92

94

96

98

100

MI (%)

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide89

Linearization of the Multi-level SVPWM in the Over-Modulation Region

SUMMARY:

  • A simple n-level PWM signal generation with linear voltage transfer characteristics throughout the modulation range, up to six-step mode of operation
  • Linear voltage transfer characteristics in the over-modulation region is achieved by modifying the reference signal such that
    • the modified reference signal has the same fundamental component as the original reference signal
    • modified reference signals are always within the carrier region
  • Inverter leg switching times are directly obtained from the sampled amplitudes of reference phase voltages signals
  • Does not require any sector identification, sine look-up tables for switching vector identification
  • Does not use sector mapping or complex timing calculations

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide91

Topology of a multilevel inverter for generation of 12-side polygonal voltage space vectors for induction motor drives.

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide92

Generation of voltage space vectors

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide94

‘Va’ positive ‘Vb-Vc’ positive: 1st quadrant

‘Va’ negative ‘Vb-Vc’ positive: 2nd quadrant

‘Va’ negative ‘Vb-Vc’ negative: 3rd quadrant

‘Va’ positive ‘Vb-Vc’ negative: 4th quadrant

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide95

If in quadrant 1:

If |Vb-Vc|<=|Va|.√3.tan150 then sector 1 else

If |Vb-Vc|<=|Va|.√3.tan450 then sector 2 else

If |Vb-Vc|<=|Va|.√3.tan750 then sector 3

else sector 4

If in quadrant 2:

If |Vb-Vc|<=|Va|.√3.tan150 then sector 7 else

If |Vb-Vc|<=|Va|.√3.tan450 then sector 6 else

If |Vb-Vc|<=|Va|.√3.tan750 then sector 5

else sector 4

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide96

If in quadrant 3:

If |Vb-Vc|<=|Va|.√3.tan150 then sector 7 else

If |Vb-Vc|<=|Va|.√3.tan450 then sector 8 else

If |Vb-Vc|<=|Va|.√3.tan750 then sector 9

else sector 10

If in quadrant 4:

If |Vb-Vc|<=|Va|.√3.tan150 then sector 1 else

If |Vb-Vc|<=|Va|.√3.tan450 then sector 12 else

If |Vb-Vc|<=|Va|.√3.tan750 then sector 11

else sector 10

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide97

V/f scheme for the drive

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide98

Comparison to obtain time durations

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide99

Pole voltage at 30Hz.

  • Voltage levels at 0.366Vdc, 1.0Vdc and 1.366Vdc are observed.

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide100

Phase voltage at 30Hz.

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide101

Pole voltage at 50Hz.

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide102

Phase voltage at 50Hz.

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide103

Fig. 14a: Phase voltage and motor current at 15Hz.

(X-axis: 1div=20ms, Y-axis: 1div=100V)

Fig. 14b: Pole voltage at 15Hz.

(X-axis: 1div=20ms, Y-axis:1div=50V)

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide104

Fig. 15a: Phase voltage and motor current at 30Hz.

(X-axis: 1div=10ms, Y-axis: 1div=50V)

Fig. 15b: Pole voltage and motor current at 30Hz.

(X-axis: 1div=5ms, Y-axis: 1div=50V)

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide105

Fig. 16a: Phase voltage and motor current at 45Hz.

(X-axis: 1div=10ms, Y-axis: 1div=100V)

Fig. 16b: Pole voltage at 45Hz.

(X-axis: 1div=10ms, Y-axis: 1div=50V)

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide106

Fig. 17b: Pole voltage at 50Hz.

(X-axis: 1div=5ms, Y-axis:1div=50V)

Fig. 17a: Phase voltage and motor current at 50Hz.

(X-axis: 1div=5ms, Y-axis: 1div=100V)

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide107

Fig. 18: Harmonics at 15Hz operation.

(X-axis: nth harmonic, Y-axis: Relative amplitude)

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide108

Fig. 19: Harmonics in 30Hz operation. .

(X-axis: nth harmonic, Y-axis: Relative amplitude)

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide109

Fig. 20: Harmonics in 45Hz operation.

(X-axis: nth harmonic, Y-axis: Relative amplitude)

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide110

Fig. 21: Harmonics in 50Hz operation.

. (X-axis: nth harmonic, Y-axis: Relative amplitude)

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide111

Control of Switching Frequency Variation in

Hysteresis Controller for IM Drives Using

Variable Parabolic Bands for Current

Error Space Phasor

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide112

Problem of Switching Frequency Variation

  • Common problems associated with the conventional, as well as current error space phasor based hysteresis controllers with fixed bands (boundaries), are the wide variation of switching frequency in a fundamental output cycle and variation of switching frequency with the variation in the speed of the load motor.
  • These problems cause increased switching looses in the inverter, non-optimum current ripple, and excess harmonics in the load current, which leads to additional heating in the motor.

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide113

Two-Level VSI fed IM Drive

Voltage Space Phasor Structure

Power Schematic

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide114

Directions of Current Error Space Phasor When Different Voltage Vectors are Switched for Different Positions of Vm in Sector-1

Start of the Sector

Middle of the Sector

End of the Sector

slide115

Factors Influencing the Switching Frequency Variation

  • Leakage inductance of the machine (L)
  • Machine voltage vector (Vm) (dominated by the back emf vectorVb)
  • DC-link voltage (as amplitude of Vk is decided by dc-link voltage)
  • Current error space phasor ripple ((i))

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide116

Variation of Switching Frequency in

Hysteresis Current Controller

  • Over a fundamental period, the position of Vm varies with respect to the inverter voltage vectors of space phasor structure.
  • Also, the selected inverter voltage vector Vk (V1, …, V8) keeps on changing in a fundamental cycle during hysteresis PWM current control.
  • Therefore, either the inverter switching frequency or/and the current error space phasor ripple will vary over a fundamental inverter period.

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide117

Variation of Switching Frequency in Hysteresis

Current Controller (Contd…)

  • For the given operating speed, if the shape of the fixed boundary of the current error space phasor is not properly selected, the switching frequency of inverter will vary over a fundamental cycle.
  • Further to this, if the same boundary of current error space phasor is maintained at different operating speeds of the machine (for different fundamental values of the machine back emf) then also the inverter switching frequency will vary.

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide118

Investigation of Current Error Space Phasor in

VC-SVPWM based VSI fed IM Drives

Typical SVPWM

switching pattern

of the inverter

voltage vectors

for two consecutive

PWM

switching intervals

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide119

Investigation of Current Error Space Phasor in VC-SVPWM based VSI fed IM Drives (Contd…)

Switching times for inverter voltage vectors in a switching interval

slide120

Investigation of Current Error Space Phasor in VC-SVPWM based VSI fed IM Drives (Contd…)

Current error space phasor during switching of various voltage vectors

Specific form for Sector-1

slide121

Movement of current error space phasor (on - plane) in a few sampling intervals of VC-SVPWM based two-level VSI fed IM drive

[Y-axis

And

X-axis:

Current

In

Amperes]

Vm at middle of the sector

( varies from 27 to 33)

Vm at start of the sector

( varies from 0 to 7)

Vm at end of the sector

( varies from 54 to 60)

slide122

Approximate theoretical boundary of i for VC-SVPWM based two-level VSI fed IM drive for position of Vm in Sector-1

[Y-axis

And

X-axis:

Current

In

Amperes]

10 Hz

20 Hz

40 Hz

30 Hz

slide128

Comparison of boundary obtained by theoretical calculations and simulation studies for VC-SVPWM based two-level VSI fed IM drive

Theoretical

10 Hz

30 Hz

40 Hz

20 Hz

0.1 A/div.

0.2 A/div.

0.2 A/div.

0.5 A/div.

Simulation

slide129

Establishing variable boundary for proposed hysteresis controller

The parabola is defined as the locus of a point which moves so that it is always at the same distance from a fixed point (called the focus) and a given line (called the directrix).

  • Formula for a vertical parabola (having Y-axis as axis of symmetry) with the vertex on (h, k), is: (x-h)2=4p(y-k).
  • Formula for a horizontal parabola (having X-axis as axis of symmetry) with the vertex on (h, k), is: (y-k)2=4p(x-h).
  • Here, p is the distance between
  • vertex and focus of the parabola.
slide130

Equivalent new X-axis and Y-axis for the parabolas of current error space phasor boundary in different sectors

CEDT, Indian Institute of Science, Bangalore, INDIA CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide131

Generalized technique to find the parameters of the boundary defining parabolas for given induction motor

(x, y),

(h, k),

p

For boundary

defining parabolas

for operating

frequency

from 1 Hz to 45 Hz

with the resolution

of 1 Hz

Vdc,

Base_freq,

L,

TS,

Generalized Technique

(Matlab Program)

Developed in Proposed Work

input

output

CEDT, Indian Institute of Science, Bangalore, INDIA CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide133

Parameters of boundary defining parabolas

for proposed hysteresis controller

CEDT, Indian Institute of Science, Bangalore, INDIA CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide135

Output of the generalized technique in terms of the current error space phasor boundary for different operating frequencies

[conventional Y-axis and X-axis: 1div.=0.5 A]

slide136

Voltage vector selection in Sector-1 for forward as well as reverse

direction of rotation of machine

CEDT, Indian Institute of Science, Bangalore, INDIA CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide137

Sector changed detection using outer parabolic boundary

[Y-axis: 1div.=0.2 A and X-axis: 1div.=0.5 A]

slide138

Sector change detection logic (based on outer parabolic bands)

for forward rotation of machine

(‘*’ means continue with the same sector)

CEDT, Indian Institute of Science, Bangalore, INDIA CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide144

Simulation results of proposed hysteresis controller

30 Hz Operation

CEDT, Indian Institute of Science, Bangalore, INDIA CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide146

Simulation results of proposed hysteresis controller

35 Hz Operation

CEDT, Indian Institute of Science, Bangalore, INDIA CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide148

Comparison of boundary obtained by theoretical calculations and simulation studies for VC-SVPWM based two-level VSI fed IM drive

SVPWM Simulation

10 Hz

35 Hz

40 Hz

30 Hz

Proposed Hysteresis Controller Simulation

slide149

Simulation results of proposed hysteresis controller

47 Hz Operation

CEDT, Indian Institute of Science, Bangalore, INDIA CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide151

Block schematic of experimental set-up used for proposed

hysteresis controller

CEDT, Indian Institute of Science, Bangalore, INDIA CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide152

Experimental results of proposed hysteresis controller

vAN, 130 V/div.

i, 0.2 A/div.

iA, 1.3 A/div.

10 Hz Operation

i, Sector-2

i, Sector-3

i, Sector-1

slide153

Experimental results of proposed hysteresis controller

iA*, 1.3 A/div.

iA, 1.3 A/div.

i, 1 A/div.

10 Hz Operation

CEDT, Indian Institute of Science, Bangalore, INDIA CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide154

Experimental results of proposed hysteresis controller

vAN, 130 V/div.

iA, 1.3 A/div.

i, 0.35 A/div.

20 Hz Operation

i, Sector-1

i, Sector-2

i, Sector-3

slide155

Experimental results of proposed hysteresis controller

iA*, 1.3 A/div.

iA, 1.3 A/div.

i, 1 A/div.

20 Hz Operation

iA, 1.3 A/div.

iA*, 1.3 A/div.

slide156

Experimental results of proposed hysteresis controller

vAN, 135 V/div.

iA, 1.3 A/div.

i, 0.45 A/div.

30 Hz Operation

i, Sector-3

i, Sector-2

i, Sector-1

slide157

Experimental results of proposed hysteresis controller

iA*, 1.3 A/div.

iA, 1.3 A/div.

i, Sector-3, 0.45 A/div.

30 Hz Operation

iA, 1.3 A/div.

iA*, 1.3 A/div.

i, 1 A/div.

slide158

Experimental results of proposed hysteresis controller

vAN, 130 V/div.

iA, 1.3 A/div.

i, 0.55 A/div.

35 Hz Operation

i, Sector-3-4, 0.55 A/div.

i, Sector-2, 0.55 A/div.

i, Sector-3, 0.55 A/div.

slide159

Experimental results of proposed hysteresis controller

iA*, 1.3 A/div.

iA, 1.3 A/div.

iA*, 1.3 A/div.

iA, 1.3 A/div.

35 Hz Operation

CEDT, Indian Institute of Science, Bangalore, INDIA CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide160

Experimental results of proposed hysteresis controller

vAN, 130 V/div.

i, 0.6 A/div.

iA, 1.3 A/div.

40 Hz Operation

i, Sector-2, 0.6 A/div.

i, Sector-3, 0.6 A/div.

i, Sector-1, 0.6 A/div.

slide161

Experimental results of proposed hysteresis controller

iA*, 1.3 A/div.

i, Sector-4-5, 0.6 A/div.

iA, 1.3 A/div.

40 Hz Operation

iA, 1.3 A/div.

iA*, 1.3 A/div.

slide162

Experimental results of proposed hysteresis controller

vAN, 130 V/div.

iA, 1.3 A/div.

i, 0.6 A/div.

45 Hz Operation

CEDT, Indian Institute of Science, Bangalore, INDIA CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide163

Experimental results of proposed hysteresis controller

vAN, 130 V/div.

i, 0.5 A/div.

iA, 1.3 A/div.

47 Hz Operation

CEDT, Indian Institute of Science, Bangalore, INDIA CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide164

Experimental results of proposed hysteresis controller

vAN, 130 V/div.

50 Hz Operation

(Six-Step Mode)

iA, 1.3 A/div.

i, 1.4 A/div.

i, 0.65 A/div.

slide165

Experimental results of proposed hysteresis controller

vAN, 130 V/div.

Acceleration Transients

iA, 1.3 A/div.

slide166

Experimental results of proposed hysteresis controller

speed, 910 rpm//div.

Starting Operation

iA, 1.3 A/div.

vAN, 160 V/div.

iA*, 1.5 A/div.

iA, 1.5 A/div.

iA, 1.7 A/div.

slide167

Experimental results of proposed hysteresis controller

speed, 910 rpm//div.

Starting Operation

iA, 1.3 A/div.

iA*, 1.5 A/div.

vAN, 160 V/div.

iA, 1.5 A/div.

iA, 1.7 A/div.

slide168

Experimental results of proposed hysteresis controller

speed, 910 rpm//div.

Speed Reversal

iA, 1.1 A/div.

iA*, 1.35 A/div.

vAN, 130 V/div.

iA, 1.5 A/div.

iA, 1.35 A/div.

slide169

Experimental results of proposed hysteresis controller

speed, 910 rpm//div.

Speed Reversal

iA, 1.1 A/div.

iA*, 1.5 A/div.

vAN, 130 V/div.

iA, 1.65 A/div.

iA, 1.5 A/div.

slide170

Salient features of the proposed hysteresis controller

  • Current error space phasor based simple hysteresis controller
  • Controls the switching frequency variation in a two-level VSI fed IM drive
  • Based on the novel concept of on-line variation of hysteresis band, depending upon the speed of the machine
  • Uses parabolic boundary for the current error space phasor
  • Obtains switching frequency spectrum in the output voltage similar to that of the constant switching frequency VC-SVPWM based VSI fed IM drive.

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide171

Salient features of the proposed hysteresis controller

(Contd…)

  • Performance of the proposed controller is independent of the load machine parameters
  • The unique parabolic boundary for different operating speeds for any given induction motor is determined using generalized technique (Matlab program) developed in proposed work
  • Calculation of machine back emf vector is not needed
  • Sector change logic is self-adaptive and is capable of taking the drive up to six-step mode of operation, if needed
  • Controller always selects the adjacent inverter voltage vectors, forming a sector, in which the tip of the machine voltage vector lies

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide172

Multimotor drive setup

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide173

Multimotor drive setup

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide175

Inverter setup for multilevel structure

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

slide176

Inverter setup for multilevel structure

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

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