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EE534 VLSI Design System Summer 2004 Lecture 06: Static CMOS inverter (CHAPTER 5)PowerPoint Presentation

EE534 VLSI Design System Summer 2004 Lecture 06: Static CMOS inverter (CHAPTER 5)

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### EE534VLSI Design SystemSummer 2004 Lecture 06: Static CMOS inverter (CHAPTER 5)

### CMOS Static Inverter design consideration

VDD

Vout

CL

Review: CMOS Inverter VTCNMOS off

PMOS res

NMOS sat

PMOS res

NMOS sat

PMOS sat

Vout (V)

NMOS res

PMOS sat

NMOS res

PMOS off

Vin (V)

PMOS in non sat

NMOS off

PMOS in non sat

NMOS in sat

PMOS in sat

NMOS in non sat

PMOS in sat

NMOS in nonsat

PMOS off

Complete voltage transfer characteristics,

CMOS inverter

Review: CMOS Inverter: VTC

PMOS

NMOS

Vin=4V

VCC

Vin=3V

Drain current IDS

Vout

Vin=2V

Vin=1V

Vin

Vout = VDS

VCC

0

1

2

3

4

- Output goes completely to Vcc and Gnd
- Sharp transition region

VDD

VDD

Rp

Vout

Vout

CL

CL

Rn

Vin = 0

Vin = V DD

CMOS Inverter: Switch Model of Dynamic Behavior- Gate response time is determined by the time to charge CL through Rp (discharge CL through Rn)

CMOS inverter operation

Vcc

- NMOS transistor:
- Cutoff if Vin < VTN
- Linear if Vout < Vin – VTN
- Saturated if Vout > Vin – VTN

- PMOS transistor
- Cutoff if (Vin-VCC) < VTP → Vin < Vcc+VTP
- Linear if (Vout-VCC)>Vin-Vcc-VTP → Vout>Vin - VTP
- Sat. if (Vout-VCC)<Vin-Vcc-VTP → Vout < Vin-VTP

Vin

Vout

CMOS inverter design consideration

- The CMOS inverter usually design to have,
(i) VTN =|VTP|

(ii) K´n(W/L)=K´p(W/L)

But K´n>K´p (because n>p)

How equation (ii) can be satisfied?

This can be achieved if width of the PMOS is made two or three times than that of the NMOS device. This is very important in order to provide a symmetrical VTC, results in wide noise margin.

CMOS inverter design consideration (cont.)

- Increase W of PMOS kp increases VTC moves to right

kp=kn

VCC

- Increase W of NMOS kn increases VTC moves to left

kp=5kn

Vout

kp=0.2kn

- For VTH = Vcc/2 kn = kp Wn 2Wp

VCC

Vin

Bad NMOS

Nominal

Bad PMOS

Good NMOS

Impact of Process Variation on VTC CurveVout (V)

Vin (V)

- Process variations (mostly) cause a shift in the switching threshold

Effects of Vth adjustment

- Result from changing kp/kn ratio:
- Inverter threshold VTH Vcc/2
- Rise and fall delays unequal
- Noise margins not equal

- Reasons for changing inverter threshold
- Want a faster delay for one type of transition (rise/fall)
- Remove noise from input signal: increase one noise margin at expense of the other

Concept of Noise Margins

VI

NML=VIL-VOL(noise margin for low input)

NMH=VOH-VIH(noise margin for high input)

CMOS inverter: VIL

- KCL: IDp=IDn
- Differentiate and set dVout/dVin to –1
- Solve simultaneously with KCL to find VIL

CMOS inverter: VIH

- KCL:
- Differentiate and set dVout/dVin to –1
- Solve simultaneously with KCL to find VIH

CMOS inverter: VIL and VIH for Ideal VTH(Symmetrical, Kn=Kp)

- Assuming VT0,n=-VT0,p, and kR = 1,

(symmetrical inverter)

CMOS inverter: VTH

- KCL:
- Solve for VTH = Vin = Vout

CMOS inverter: Ideal VTH (Symmetrical, Kn=Kp)

- Ideally, Vth = VCC/2
- Assuming VT0,n = VT0,p,

For ideal symmetrical inverter required that

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