EE534 VLSI Design System Summer 2004 Lecture 7: Static Dynamic CMOS inverter (CHAPTER 6). Calculation of Delay times: Average current method. The average current during high to low transition can be calculated by using the current values at the beginning and the end of the transition.
EE534VLSI Design SystemSummer 2004 Lecture 7: Static Dynamic CMOS inverter (CHAPTER 6)
The average current during high to low transition can be calculated by using the current values at the beginning and the end of the transition.
The average current during low to high transition can be calculated by using the current values at the beginning and the end of the transition.
Review: Propagation delay simulation results
At very short channel width, the delay approaches a limit value of about 0.2nsec
, which is mainly determined by technology-specific parameters, independent
of extrinsic capacitance component.
CMOS Ring Oscillator Circuit
CMOS Ring Oscillator Circuit (cont.)
T=PHL1+PLH1+ PHL2+PLH2+ PHL3+PLH3
=2 P+ 2P+ 2P
Delay estimation using switch-level model (for general RC circuit):
Standard RC-delay equations
CMOS inverter Power Dissipation
Lead microprocessors power continues to increase
Power delivery and dissipation will be prohibitive
Source: Borkar, De Intel
…chips might become hot…
Power Density (W/cm2)
Source: Borkar, De Intel
Drain junction leakage
Sub-threshold current is the dominant factor.
All increase exponentially with temperature!
Case I: When the input is at logic 0: Under this condition the PMOS is conducting and NMOS is in cutoff mode and the load capacitor must be charged through the PMOS device.
Power dissipation in the PMOS transistor is given by,
The current and output voltages are related by,
Similarly the energy dissipation in the PMOS device can be written as the output switches from low to high ,
Above equation showed the energy stored in the capacitor CL when the output is high.
Case II: when the input is high and out put is low:
During switching all the energy stored in the load capacitor is dissipated in the NMOS device because NMOS is conducting and PMOS is in cutoff mode. The energy dissipated in the NMOS inverter can be written as,
The total energy dissipated during one switching cycle is,
The power dissipated in terms of frequency can be written as
This implied that the power dissipation in the CMOS inverter is directly proportional to switching frequency and VDD2
Not a function of transistor sizes!
Data dependent - a function of switching activity!
Function of fan-out, wire length, transistor sizes
Has been dropping with successive generations
Pdyn = CL VDD2f
Finite slope of the input signal causes a direct current path between VDD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting.
Imax: depends on saturation current of devices
Psc = tsc VDD Ipeak f01
Large capacitive load
Output fall time significantly larger than input rise time.
Small capacitive load
Output fall time substantially smaller than the input rise time.
When load capacitance is small, Ipeak is large.
CL = 20 fF
CL = 100 fF
Short circuit dissipation is minimized by matching the rise/fall times of the input and output signals - slope engineering.
CL = 500 fF
500 psec input slope
When load capacitance is small (tsin/tsout > 2 for VDD > 2V) the power is dominated by Psc
VDD= 3.3 V
VDD = 2.5 V
If VDD < VTn + |VTp| then Psc is eliminated since both devices are never on at the same time.
VDD = 1.5V
W/Lp = 1.125 m/0.25 m
W/Ln = 0.375 m/0.25 m
CL = 30 fF
normalized wrt zero input rise-time dissipation
For a design with I million gate
Is this possible in reality? If not why?
Pdyn=Edyn/2tp=580W for tp=32.5ps
Pdyn=Edyn/2tp=155W for f=4GHz(250ps)
(Lower-power and Robust)