ENTS641 - Topic 3: Switching

1. 1 ENTS641 - Topic 3: Switching Dr. Asha Mehrotra 2/23/01 � 3/2/01

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3. 3 Introduction

4. 4 Performance Measure Performance measures for a switch are: (a) connectivity, (b) delay and call setup time, (d) Capacity, and (f) complexity (g) Call blocking and Packet loss rate - Connectivity is measured by the set of pairs of input and output links that can be simultaneously connected through the switch. The larger this set, the more versatile the switch. As it processes incoming bit streams in order to route them to the proper output ports - the switch introduces delays, and this delay is another measure of performance. For circuit switches, one component of delay is the switch setup time. For packet switches, the equivalent is queuing delay.

5. 5 Performance Measure (Contd.) - The capacity of a switch is the maximum rate at which it can move information, assuming all data paths are simultaneously active. The primary requirement of a switch is to maximize capacity for a given cost and a given reliability. - Measures to estimate the complexity of a switch include the number of cross points (circuit switch), and the buffer size (packet switch)� - A circuit switch must reject a call if it does not have a path from an input to an output to carry the call, since it cannot buffer data. This is called call blocking. In a packet switch, data can be stored in a buffer, so call blocking is not a concern. Instead, the analog of call blocking is packet loss, that is, the loss of one or more packets because of a buffer overflowing when a burst of packets arrives at the switch.

6. 6 Switch Representation One representation of a switch is a �black box� shown at the top of the figure in the next page. Here, switch is a advice with M input and N output links. The second representation can be a �cross bar� where the complexity is measured in terms of number of cross points (M x N). The cross point can either be open or closed. In the figure input-output pairs (1,2), (2,1) , and (M, N) are closed. Rest of the cross points are open. The bottom figure represents a multi-stage switch where the input is not directly connected to output but indirectly connected through some number of middle stages. A generic switch shown below consists of four parts: (1) Input buffers; (2) Port mapper; (3) Switch Fabric; and (4) Output buffers Input Buffer: Input buffers store packets or samples as they arrive on the input lines. Some switches have tiny input buffers that hold data only while it is contending for the switch fabric. Other switches have almost all their buffers at the inputs

7. 7 Switch Representation The port mapper reads either the destination address or a virtual circuit identifier from an incoming packet's header and uses a table to decide the packet's output port. A circuit switch does not need a port mapper because each time slot is automatically associated with a path from an input to an output. The switch fabric routes data from an input to an output. The simplest switch fabric is a processor that reads data from an input port and writes it to an output port. Switch fabrics can also be complex multiprocessor systems that simultaneously transfer thousands of packets along many parallel data paths. Output buffers store data as they wait for a turn on the output line. At each output port, a scheduler manages the output buffers and arbitrates access to the output line. As with input buffers, these can be small or large. Some switches distribute, combine, or omit one or more of these functions. For an example, a switch may combine the input and output buffers, distribute the port mapper among the input ports, or omit the input buffers.

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10. 10 Single Stage Cross Bar Matrix As shown above for M = N, the number of cross points required is N x (N-1). This is essentially a non-blocking matrix which implies that so long as the input output ports are free a path can always be completed. However, as N increases the number of required cross points can be excessively high. The number of cross points can be reduced to half i.e. N(N-1)/2 by going through a triangular array (still non-blocking). However, for large value of N the number of cross points can be prohibitively large. Therefore, both the multiple stages of matrix as well as some controlled amount of blocking can be introduced to reduce the number of cross points as discussed below. We will explore the case of multiple stage matrix Multiple stage switching: Following advantages can be obtained by implementing multiple stage of matrix: Reduction of number of cross points Reduction of capacitive loading (now there are not too many cross points from one inlet or one outlet) Specific cross point need not be operated going from one input to one output

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12. 12 Multistage switching

13. 13 Non blocking condition for three stage matrix In 1953 Charles Clos of Bell Laboratories published an anlysis of three-stage switching networks showing how many center stages are required to provide a strictly non-blocking operation The worst case condition arises when (n-1) center stages are busy from the first stage, and the second set of (n-1) center stages are busy due to third-stage array. Thus, the total number of non available sets are: (2n-2). Under this condition if there is one more center stage then the appropriate input can be connected to output provided both the input and the output are idle. Thus, for non-blocking condition K = 2n-1; and the number of cross points are:

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15. 15 Non blocking condition for three stage matrix

16. 16 Non blocking condition for three stage matrix

17. 17 Time-Division Switches Figure below illustrates the operations of time division switch. The top part of the figure shows N input signals that arrive on N different links(channels). These signals are periodic bit streams that must go out on different output links(channels). In the figure it is assumed that the signal arriving on link 1(channel 1) must go out on link N (channel N), that arriving on link 2 (channel 2) must go out on link 1(channel 1), . . ., and the signal arriving on link N (channel N) must go out on link 3 (channel 3). The time-division switch has three parts: a time-division multiplexer (MPX), a time-slot interchanger, and a time-division de-multiplexer (DMX). The MPX first multiplexes the N incoming signals. The multiplexed signals arrive at the slot interchanger, which writes the successive slots into N distinct buffers as shown. The output line of the time-slot interchanger then reads the N buffers in the order 1 2 .. .. N. The output of the slot interchanger is then de-multiplexed into N different signals that are sent to the (different) output links (channels). Note that the delay from the time the signal arrives on an input link until it is placed on the output link is two frame duration. Assuming the bit rate of each link to be b bps, the total bit rate of the switch is N x b pbs. Detailed memory operation (Time slot interchange circuit:- Ref. Bellamy) is shown below.

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19. 19 Time Division switch

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21. 21 Time-Space-Time Switch To achieve greater throughput than possible by time-division alone, one can combine it with space division switch. The conceptual diagram and one possible implementation is shown below. The exact realization shows that the information arriving in a TDM channel of an incoming link is delayed in the inlet time stage until an appropriate path through the space stage is available.

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29. 29 Blocking in Packet Switches In a packet switch, as with a circuit switch, we can have both internal blocking and output blocking. A blocked packet is either dropped or buffered. In a circuit switch, if two circuits block each other, the switch must reject one of them. On the other hand, in a packet switch, even if packets a and b on connections A and B block each other, subsequent packets on A and B may not block each other. Thus, it is impossible to predict whether the individual packet will be blocked or not. However, in reality packet will be blocked and the minimization of blocking loss is essential. Following techniques can be used to minimize the blocking loss - Overprovisioning: By making internal links faster than inputs, the switch fabric can forward packets from more than one input in the time it takes for a single packet to arrive. - Buffers: By placing buffers at the input or in the switch fabric, we can delay packets that do not enter the switch fabric until a link is available.

30. 30 Blocking in Packet Switches(Contd.) - Backpressurc: Backpressure allows a stage in a multistage switching fabric to prevent the previous stage from sending it any more data. If an output is blocked, backpressure signals quickly propagate back to the input, forcing packet buffering and packet loss to happen only at the inputs. Thus, with backpressure, the switch fabric needs only a minimal amount of buffering. - Sorting and randomization: Preceding the switch fabric by a sorting or randomization stage reduces internal blocking in the fabric. - Parallel Fabrics: By connecting input ports to output ports with multiple parallel switching fabrics, packets can be carried from inputs to outputs m parallel. This reduces contention for the fabric, but requires faster access to output buffers.

31. 31 Important Switch Fabric Packet switch fabric is a set of links and switching elements that transfers a packet from any input port to any output port. Following are in order for study Crossbar Broadcast Switching Element Distributed buffer switches based on basic switching element

32. 32 Crossbar Switch The simplest switch fabric is a crossbar shown below. An N � N crossbar has N input buses, N output buses, and N2 cross points, which are either on or off. If the (i, j) cross-point is on, then the ith input is connected to the jth output. A crossbar is internally non-blocking. A crossbar needs a switching schedule that tells it which inputs to connect to which outputs at a given time. If a switch has N inputs and outputs, a perfectly used crossbar is N times faster than a bus-based switch. However, if two packets at the inputs are destined for the same output they suffer from output blocking We can avoid output blocking by either running the crossbar N times faster than the inputs (which is hard to do, and expensive), or placing buffers inside the crossbar. One interesting variation is to put a buffer at every cross point. An arbiter per output line then decides which of the buffered packets to serve.

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34. 34 Broadcast Switch Tine broadcast switch shown in Figure below tags a packet arriving at any input with the output port number and broadcasts it to all outputs. �Each output port stores incoming packets that match its own port address ill an output queue. A scheduler resolves contention for the output trunk. �Since the switch broadcasts all packets to all output ports, a small change makes it easy to implement hardware multicast. Instead of matching port addresses, each output port matches a packet's VC1. At the time of call setup, each port is informed of the VCIs it must match, and at the time of data transfer, each port matches a packer's VCI with its list of eligible VCIs. �In an N � N broadcast switch, each output must be connected to N buses, and it needs to do an address match on packets arriving at all the inputs. For a thousand-port switch, each port needs to be connected to a thousand inputs, which becomes a physical routing problem.

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36. 36 Switch Fabric Element Complex switch fabrics using a basic fabric element consisting of two inputs, two outputs, and an optional buffer is shown in figure below. Operation of the switch is based on two inputs and can be as follows Example, if the packet has a l-bit header, the rule might be: forward on the upper output if the bit is 0, and on the lower output if the bit is 1. If both packets at the inputs want to go to the same output, then one of them is forwarded, and the other is either buffered or dropped. We can generalize an element to N inputs and outputs as follows: For an N x N switch, if each element switches b x b lines, then the switch has ?logbN? stages, with ? N/b? elements per stage. For example, a 4096 X 4096 switch built with 8 x 8 blocks has four stages, with 512 elements in each stage.

37. 37 Switch Fabric Element Once a packet has been labeled with the correct output port, it will automatically make its way from any input to its correct output. This is called self - routing. The fabric is recursively composed from smaller components that resemble the larger network. In other words, the topology of a fabric with bN elements is similar to that of a fabric with N elements and is built from b fabrics with N elements each The fabrics are regular and suitable for VLS implementation.

38. 38 Distributed Switch Four �delta� network based on the above discussion is shown below. These are arrangements of 2 x 2 crosspoint modules If there are N = 2n input and output ports, there are N/2 rows and n = log2 N stages, for a total of N/2log2 N modules, hence 2N log2 N crosspoints. Note that each module contains its own buffer as discussed above and hence the name distributed buffer. All four networks are similar except the routing from input to output is based on different rules A cell arriving at a switch input port consists of two parts: data and tag The tag contains the destination the VCI. This tag is read by the switch controller, which determines the output port to which the cell must be routed.

39. 39 Distributed Switch Having determined the output port, the switch controller replaces the arriving tag by an internal tag that designates the output port. So this tag is a sequence of n = log2 N bits. These bits are used one at a time by the log2N stages of 2 x 2 modules to determine whether the cell should go "up� or "down�. In the illustration of the figure, n = 3, so the tag = b3b2b1. In the first stage, bit b1 is examined by the input port and decoded to determine whether the cell goes up or down. Bit b1 is then stripped. Similarly, at stage 2, bit b2 is decoded and lastly, in stage 3, bit b3 is decoded. The cell, stripped of its tag arrives at the proper output port designated by b3b2b1

40. 40 Distributed Switch While the cell is being routed through the switch fabric, thc switch controller calculates the new tag from the routing table. It is appended to the outgoing cell. Figure below illustrates the banyan network. The top of the figure gives the routing rule. The rule is: if the output port is ABC, the tag is CAB; again bit 1 is down and 0 is up. The figure shows the routes from the two input ports to two output ports 100 and 001. Note the conflict showing the hot spot within the switch.

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44. 44 Packet Switch (ATM) We discussed the general scheme of packet switching last time. This is shown in the next page diagram Cell at the input has data plus Tag. Tag is read by the switch controller which determines the desired output port to which the cell must be routed (successful packet, no collision) The first action the switch controller does is to replace the input tag by an internal tag that designates the output port. This tag is the sequence of n bits, where n = log2N, Where N is the number of input and output ports. First bit b1 is examined and decision to move up or down made. The first bit is then stripped and second bit is examined which makes move to the second stage and so on till the packet stripped of all its tags arrives at the output. While the cell is being routed through the switch fabric, the switch controller calculates the new tag from the routing table. It is appended to the outgoing packet (cell). Similar to the case of Clos matrix in circuit switching the idea of all multistage connection networks (MINs) is to implement larger switch fabric from smaller switch elements in a modular fashion. Where the smaller switch element can be a cross bar. The interconnection between switch stages follow certain rule as shown below for Banyan network. The implementation of these switches are easily achieved in VLSI circuits.

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46. 46 Banyan Network A MIN has the following property: There is exactly one path from any input to any output Delta network = Banyan network with self-routing property Interconnection between stages follow the concept of deck shuffling of playing cards. Q-shuffle of qr playing cards follows the rule that qr playing cards are divided into q piles of r cards each; top r cards in the first pile, next r cards in the second pile and so on. Now pick the card s, one at a time from the top of each pile; the first card from the top of pile one, the second card from the top of pile two, and so on in acircular fashion until all cards are picked up. This new order of cards represent the q-shuffle of the previous order. Mathematically the q-shuffle of qr objects, denoted as Sq*r, where q and r are positive integers is a permutation of qr labels 0,1,�.qr-1 defined as: Sq*r(i) = qi mod(qr-1) if 0? i <qr-1 = i if i = qr �1 An example of 4-shuffle (four cards in one group) of 12 objects are shown below

47. 47 4-Shuffle of 12 Objects Example: 4-shuffle of 12 objects. Here, qr = 12 and q = 4 Now applying the equation qi mod (qr-1). Now vary i from 0 to 11. Obviously, 0 maps to 0. i =1 maps to 4 x 1mod(11) = 4. Similarly, 5 will map to 20 mod(11) or 9. Interconnection between Banyan is 4-shuffle and Two-two shuffle as shown below. Thus, for the first stage qr = 8, q = 4 and and the values of i between (0 , 7). Thus # 3 output of first stage (i= 3) maps to: 4 x 3 mos(7) = 5. Verify the rest yourself. Note that the configuration is such that both the inputs to middle and the last stage are either from the top or the bottom of the previous stage. This rule applies to all configurations shown in figure below. Observation of interconnection for omega network suggests that q = 2. Thus, it is 2 shuffle of 8 objects. Thus, you divide inputs into four groups of 2 each and apply the concept of deck shuffling. Thus, when i =5; you map to 2 x 5 mod(7) or 3. Apparently, under certain input conditions there can be conflict as shown by the hot spot in the figure below.

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51. 51 Impact of Hot Spots Let p(m) represent the probability that a cell is forwarded over a link of the DBS after going through m stages, in one slot. Let p(0) = 1, since an external cell arrives at each input link in each time slot. The probability that a cell is not forwarded over (m+1)st link is given by 1-p(m+1). This can only happen when no cells arrive here from either of the two inputs. The probability that a cell is routed from link A to C is 0.5p(m), so the probability that a cell is not routed from A to C is [1- 0.5p(m)]. This is also the. probability that a cell is not routed from B to C. Since these two events are independent, the probability that no cell is routed to C from A or B is given by: [1 - p(m+1)] = l- [1 - 0.5p(m)]2; p(0) = 1 or, p(m+1) = 1-p(m) +(1/4) p2(m) Recursive equation in m can be solved for different values of m; Thus for m =0, p(1) = 1-1+1/4 = � , Similarly, p(2) =0.62, p(3) =0.52, p(4) = 0.45 Figure below shows that the successive stage output decreases as m increases. In other words the probability of conflict is high and the link output is lost due to conflict. To avoid this decline in throughput the module must have buffer (Conclusion)

52. 52 Buffered Banyan Network As seen above the blocking occurs if two incoming packets want to go to the same output terminal of a switching element Solution, include buffer in every switching element. Expensive solution To avoid packet loss, buffer size must be large enough to hold the worst case pattern Under uniform traffic throughput is limited to 45% with a single buffer. It can be shown that 4 buffers will increase the throughput to ? 60% Since buffering is an expensive solution let us first try to minimize hot spots by other innovative techniques. Two techniques are perused: (a) Use of randomization stage in front of Banyan switch, (b) Use of sorting network in front of Banyan switch. Let us discuss each of these one by one

53. 53 Use of Randomization stage The technique is shown in Figure below. Here, an additional banyan switch is added in front called the randomization stage. When a cell arrives at an input port, its destination output port, Out, is replaced by another destination port, Ran. The new destination port is randomly selected with a uniform distribution over all N output ports. On leaving the randomization stage, each packet's original destination Out is restored, and it enters the second switch at input port Ran. In the first stage, the probability distribution of the sequence of destination vectors is independent from one time slot to the next and uniformly distributed over the output ports. Thus, links inside the switches will on the average carry an equal number of packets. This will minimize hot spots within the switch The second stage randomization is a mirror image of the first stage. Here, for the destination output port for any cell, the input port from which that cell originates is independent from one interval to the next and thus uniformly distributed over the N input ports. This will also reduce the number of hot spots in the second stage links. Since randomization is statistical, this technique does not completely eliminate all hot spots, and thus, buffer at each stage will be required.

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55. 55 Batcher Banyan Network The technique is based on the observation that if the destination N-vector if sorted (in increasing order) by output port, the corresponding N routes will be disjoint. As shown in the figure cells in the first two input ports have destinations 110 and 111, so they are sorted. With this sorting the two routes have no links in common, so both cells can be transmitted simultaneously, and there will be no contention or need for buffers within elements. Thus the Banyan network is preceded by sorting network. Sorting in the Batcher network follows the rules shown in Figure below. However, if two input cells with the same destination output port appear at the Batcher network, there will be contention. So one of those cells cannot be allowed to enter the network and must be buffered. Thus a Batcher-banyan switch also must be equipped with buffer

56. 56 Bitonic Sorters Figure above is a 2-bitonic sorter which is just a simple comparator. The definition of monotonic and bitonic sequences are: A monotonic sequence is a sequence of numbers that is either increasing or decreasing. E.g. (1,4,5,7,7,9) A bitonic sequence of length 2n is made up of two consecutive monotonic sequences of length n: one increasing and the other decreasing. E.g. (1,4,5,9,7,6), (9,7,6,1,4,5)

57. 57 Shared Buffer The shared buffer design is exclusively based on software control and manipulation in memory. There is a common pool of buffers divided into linked lists indexed by the output port name as shown below. There is also one linked list of free buffers. Each list has a begin and end pointer. The switch operates as follows. In each time slot the following operations take place: First, a cell from the beginning of each linked list is transmitted over the corresponding output port. The list's begin pointer is updated, and the buffer (due to link list moving forward) is added to the free buffer list. Second, the new cell arrived at the input ports during the time slot are examined. If a cell is destined for output port i, it is put in a free buffer (whose begin pointer is moved up) and that buffer is appended to the list for port i.

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59. 59 Shared Buffer Advantage: Here, there is a common pool of buffer instead of buffer associated with the individual stages of the realization as discussed above. Thus, the effectiveness is more. In other words for the same blocking probability the buffer required is less or for the same overall buffer the blocking probability is reduced. Software having more flexibility can easily associate priorities with the output � Disadvantages: Maximum speed of operation can equal sum of all inputs N. In other words speed of operation can be N times higher than the input/output. In each time slot, one cell per input port has to be read into the buffer, and one cell per output port has to be read out. If buffers are implemented in RAM, then their speed may place a limit on the maximum throughput. - Also, for multicast operation each link list has to be updated. The cell for broadcast must be added to different output ports

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61. 61 Shared Buffer

62. 62 ATM Switch: Output Buffer Incoming cells are multiplexed over a fast bus and then passed through an address filter to find the destination output port. Cells destined for specific output is included in the associated buffer. Advantages: Provides better buffer utilization than the distributed buffer design but a lower buffer utilization than the shared buffer design. Best suited for multicast operation Disadvantages: The bus speed must be as large as the sum of the input link speeds. The speed of operation of output buffer can impose limitation on the number of inputs which can be destined to a specific output. If only K inputs out of N ( K <N) are allowed to go to a specific output some fraction of the input destined for a specific output is dropped. Various procedures exist for making sure that each of the M cells has the same probability of being selected, for fairness. One such scheme--called the knockout switch-implements a K-stage knockout tournament.

63. 63 ATM Switch: Output Buffer The designer must choose the value of K that keeps the fraction of dropped cells to an acceptable small value. Assuming that there is a cell arriving at each input link with probability ?, independently of the other input links. The probability that M cells arrive in one time slot and are destined to a specific output link is then equal to P(M) and is given by:

64. 64 ATM Switch: Output Buffer

65. 65 Summary of Switching Switching types: circuit switching, connectionless and connection oriented switching Performance measure Switch representation Circuit switching: Single stage cross bar matrix, multistage switching nonblocking (3 stage), time division switching Datagram switching: concept of the router (trie) Blocking in packet switching Switch fabric for ATM: Crossbar, Broadcast, Distributed buffer switches Basic elements of switches Types of switches: Banyan, Omega, Baseline and flip switches--Tagging concept Interconnection analysis-- Shuffling concept Hot spot concept and its impact in throughput Hot spot fix: randomization, and sorting--Bitonic sorter Shared buffer analysis Output buffer analysis