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Electronics for large LAr TPC’s. F. Pietropaolo (ICARUS Collaboration) CRYODET Workshop LNGS, 13-14 March 2006. Outline. The ICARUS front-end electronics Layout in T600 module (analogue + digital) Performance and limitations Possible upgrades for multi-kton detectors

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Electronics for large LAr TPC’s

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Electronics for large lar tpc s

Electronics for large LAr TPC’s

F. Pietropaolo (ICARUS Collaboration)

CRYODET Workshop

LNGS, 13-14 March 2006



  • The ICARUS front-end electronics

    • Layout in T600 module (analogue + digital)

    • Performance and limitations

    • Possible upgrades for multi-kton detectors

  • Alternatives solutions

    • Front-end inside vs outside LAr

    • Analog-to-digital serial converter

  • Summary

CryoDet workshop, LNGS

The icarus t600 experience

The ICARUS T600 experience

  • The T600 DAQ system (5·104 channels), designed in Padova, engineered and built by CAEN, has proven to perform satisfactory during the 2001 test run in Pavia.

  • It consists of an analogue front-end followed by a multiplexed AD converter (10 bit) and by a digital VME module performing local storage, hit finding and data compression.

  • From the experience gained with the T600 operation, an R&D phase is underway in view of an upgrade for a multi-kton detector with ~ n·105 channels (better S/N, larger integration, lower cost).

CryoDet workshop, LNGS

The icarus read out principle

The ICARUS read-out principle

m.i.p. ionization

~ 6000 e-/mm


Edrift ~ 500 V/cm

Drift direction








n x 4kB


circular buffer

Low-noise amplifiers




To storage



CryoDet workshop, LNGS

The induction signals

The induction signals

Ionizing track

Induced currentInduced charge






u-t view


Induction 1

v-t view



Induction 2

w-t view


= ampl.


= area




Drift timeDrift time

  • ICARUS T600: three wire planes (pitch 3mm, separation 3mm)

Edrift = 500 V/cm

Mip signal ~ 12000 e- (inc. recombinantion)

Electron drift velocity ~ 1.5 mm/s

Typical grid transit time ~ 2-3 s

CryoDet workshop, LNGS

Requirements for the preamplifier

Requirements for the preamplifier

  • Need of very low noise amplifier:

    • No amplification around sense wires

      • Induced charge ~ 104 electrons

    • Large input capacitance (CD)

      • Wires (20 pF/m) + cables (50 pF/m)

      • In T600 CD ~ 300-400pF

      • Serial noise (proportional to CD) dominates over parallel noise (proportional only to signal bandwidth)

    • High trans-conductance (gm) input device required to ensure acceptable Signal-to Noise level (S/N ~ 10)

CryoDet workshop, LNGS

Choice of the active input device

Choice of the active input device

  • Bipolar transistors

    • gm ≈ 400mS @ Ic ≈ 10 mA (Amplification merit factor gm·Zout ≈ 3-4·105)

    • BUT: parallel noise density ≈ 2 pA / √Hz too high (with a typical LAr signal bandwidth of ~ 1 MHz gives unacceptable noise contribution)


    • Extremely low gm

  • jFET

    • Good gm ≈ 40mS @ Ids ≈ 10 mA (Amplification merit factor gm·Zout ≈ 3-4·104)

    • negligible parallel noise density ≈ 0.001 pA / √Hz

ICARUS choice since 1986:

charge sensitive preamplifier with high gm jFET input stage

CryoDet workshop, LNGS

The icarus t600 preamplifier

The ICARUS T600 preamplifier

Two versions:

“quasi-current” mode: RfCf ≈ 1.6s (collection +

first induction)

“quasi-charge” mode: RfCf ≈ 30s (mid induction)

  • Custom IC in BiCMOS technology

    • Classical Radeka integrator

    • External input stage jFET’s

      • Two IF4500 (Interfet) or BF861/2/3 (Philips) in parallel to increase gm (50-60 mS)

    • External feed-back network

      • Allow sensitivity and decay time optimization

      • High value f.b. resistor (100M) reduce parallel noise

    • External baseline restorer circuit

  • Two channels per IC

    • Identical symmetrical layout guarantees identical electrical behavior

Sensitivity ≈ 6 mV/fC

Dynamic range > 200 fC

Linearity < 0.5% @ full scale

Gain uniformity < 3%

E.N.C. ≈ (350 + 2.5 x CD) el ≈ 1200 el. @ 350pF

Power consumption ≈ 40 mW

CryoDet workshop, LNGS

Layout of front end electronics

Layout of front-end electronics

H.V. (<±500 V)




VME board (18/crate)

Liquid argon Gas

Sense wires

(4-9m, 20pF/m)

4 Multiplexers

(400ns x 8ch.)

Twisted pair cables

(~5m, 50pF/m)

10bit FADC

400ns sampling


Front-end amplifiers




(32 ch.)

ICARUS T600: ~ 54000 channels — 1720 boards — 96 crates

Cost of the full electronic chain: ~ 80 € / channel

CryoDet workshop, LNGS

The icarus t600 read out chain

The ICARUS T600 read-out chain

CAEN-V789 board: 2 Daedalus VLSI * 16 input channels (local self-trigger & zero suppression) + memory buffers + data out on VME bus

Signal UHV feed-through:

576 channels (18 connectors x 32)

+ HV wire biasing

Decoupling board: HV distribution and signal input

CAEN-V791 board: 32 pre-amplifiers +

4 multiplexers (8:1) + 4 FADC’s (10 bits - 20 MHz)

CryoDet workshop, LNGS

The t600 electronic racks

The T600 electronic racks

CryoDet workshop, LNGS

The analogue board v791

The analogue board V791



Digital link


BiCMOS IC layout

Input signal connector

Output of analogue sum

Shielding of front-end

CryoDet workshop, LNGS

Performance of the v791 boards

Performance of the V791 boards

128 wires/view

1024 samples

400 ns/sample



Mid. Induction


1st Induction

1st Induction

CryoDet workshop, LNGS

Performance of the v791c board

RMS noise on T600 = 1.3 - 1.7 ADC counts (due to difficult environment in Pavia)

Performance of the V791C board

  • Single wire waveforms (horiz. axis unit = 400 ns)

Test pulse

(6 mm m.i.p)

24 ADC counts

FWHM ≈ 5 µs

m.i.p. ≈ 12 ADC counts

(3 mm) FWHM ≈ 5 µs


1st Induction

Noise RMS ≈ 1.3 ADC counts

Coherent noise due to layout not negligible!

CryoDet workshop, LNGS

Performance of the v791q board

Pulse height & shape from mid. plane wires very similar to those from collection plane wires.

High frequency S/N also comparable.

Low frequency minimized by baseline restorer.

Performance of the V791Q board

  • Single wire waveforms (horiz. axis unit = 400 ns)

Mid. Induction

Test pulse

(6 mm m.i.p.)

24 ADC counts

RC ≈ 30 µs

m.i.p. ≈ 10 ADC counts

(3 mm) FWHM ≈ 5 µs

Noise RMS (h.f.) ≈ 1.2 ADC counts

Low frequency noise visible but not dangerous!

CryoDet workshop, LNGS

Events from t300 semi module

Collection view

Events from T300 semi module

Drift time (1.5m)

Wire numbering (4.5m)

Induction2 view

Drift time (1.5m)

Wire numbering (4.5m)

CryoDet workshop, LNGS

Possible upgrades

Possible upgrades

  • In a multi-kton LAr-TPC with the ICARUS read-out principle we can foresee

    • S/N close to T600

      • Longer electrodes (larger input capacitance, more electronic noise)

      • But probably larger electrode pitch (more input charge)

    • Larger number of channels (~ n•105)

      • Require integration, cost reduction

  • Present overall architecture fully satisfactory

    • Improvement will focus on

      • Input stage jFET

        • Technology still state of the art

        • Optimization of number of input jFET to larger input capacitance

      • Review IC design - Integrate more channels

        • BiCMOS technology evolved since last IC design

        • Careful study of layout topology

      • Development of new hybrid sub module

        • Hosting more amplification channels (e.g. 4 - 8)

        • And, possibly, the analogue-to-digital converter stage

  • CryoDet workshop, LNGS

    Electronics in lar

    Electronics in LAr

    • Deeply investigated within ICARUS collaboration (since 1988)

    • Limited choice of active devices working at LAr temperature

      • GAs-jFET (High Electron Mobility Transistor technology)

      • Silicon jFET (High Resistive Substrate technology)

      • Expected characteristics:

        • Better S/N due to improved gm at cryogenic temperature

        • Reliability at LAr temperature

        • Availability on the market

    U310 jFET

    Carrier mobility decrease

    Pinch-off increase

    CryoDet workshop, LNGS

    Pro contra

    Pro & Contra

    • Advantages

      • Reduction of input capacitance due to cable absence

      • Reduction of micro-phonic noise (detector = Faraday cage)

      • Intrinsic improvement of S/N due to larger jFET gm at cryogenic temperature

    • Disadvantages

      • Inaccessibility during detector operation

      • Need of careful selection of components, extensive burn-in and temperature cycles before installation to minimize components failure

      • Design architecture and technology restricted by limited choice of active components

      • Limit on power dissipation (< 100 mW/mm2 to avoid LAr boil-off)

    CryoDet workshop, LNGS

    The totem architecture

    The TOTEM architecture

    • Charge Integrator made on Thick Film Hybrid technology with discrete jFET only

      • Minimum active and passive components

      • Ability to drive long transmission line

      • Reduced power consumption

      • Minimum cable connections

        • Current signal from Positive Power Supply

        • Common Negative polarization

    • Characteristics

      • Optimized for low detector capacitance


    Sensitivity ≈ 0.45 mV/fC (0.9 A/fC)

    Dynamic range ±1.5 pC

    Linearity < 0.5% @ full scale

    Input impedance ≈ 420 

    Input capacitance ≈ 20 pF

    E.N.C. ≈ (390 + 7 x CD) el

    Power consumption ≈ 11 mW

    CryoDet workshop, LNGS

    Events with electronics in lar

    Events with electronics in LAr

    • Extensively used on the 50 liter LAr-TPC

    • Wire capacitance: ~ 15 pF

    (horiz. axis unit = 400 ns)


    mip ≈ 10 ADC

    counts (2.54 mm)

    FWHM ≈ 6 µs


    Noise RMS ≈ 0.7 ADC counts


    Negligible low frequency noise !

    CryoDet workshop, LNGS

    The icarus experience

    The ICARUS experience

    • Electronics in LAr studied for sake of completeness

      • Not a viable solution for large scale detectors

        • Inaccessibility, poor integration, cost

    • However

      • TOTEM design could be improved

        • HEMT replacing silicon jFET

        • jFET matrix on single chip

          • Technology commercially available for low temperature application

          • E.g. INTERFET IPA300 amplifier (serial noise density = 0.6 nV / √Hz, 80 mW dissipation)

    CryoDet workshop, LNGS

    Analog to digital conversion

    Analog-to-digital conversion

    • Two sets per V789 board (32 ch.)

      • Total bandwidth = 800 Mbit/s

    • Present architecture

      • Serves sets of 16 channels through analogue multiplexers and 10 bit FADC’s

      • Trade-off between sampling speed and price

    • FADC sampling rate 20MHz interleaved

      • 400 ns sampling time / channel

      • 40MHz digital output

    • Dissipated power ~ 500 mW

    • Components cost ~40 € / 16 channels

    CryoDet workshop, LNGS

    Compact serial ad converter

    Compact serial AD converter

    • New architecture based on 1-bit serial converter

      • Interesting characteristics

        • No need for multiplexing

        • Very low number of components

        • Resolution better than 10 bit

        • Commercially available chip

        • Low price (< 1 € / channel)

      • Basic structure

        • Four QUAD FLATPACK 4x4 mm2 components plus few glue logic

        • Sampling rate = 16 MHz

        • Dissipated power = 400mW

    • Data reconstruction

      • Simple FIR filters could be implemented

        • In pipeline on FPGA / DSP

        • Off line after data storage

      • Serving multiples of 16 channels

    • Test underway of 16 channel prototype boards fully compatible with present ICARUS data link

      • Total bandwidth = 256 Mbit/s

        • Upgradable to 800 Mbit/s if sampling rate increased to 25 MHz and 32 channels

    CryoDet workshop, LNGS

    Serial adc frequency response

    Serial ADC frequency response

    16 sample FIR comb filter equivalent to 10 bit resolution

    8 sample FIR comb filter equivalent to 8 bit resolution

    25 MHz

    16 MHz

    Typical ICARUS signal bandwidth (~ 1 MHz) better matched in 25 MHz case.

    Marginal in the 16 MHZ case

    CryoDet workshop, LNGS



    • Typical ICARUS signal waveform (~3s width) digitized with Serial AD converter

    • FIR comb filter applied to recover signal shape (16 sample width)

      • 10 bit equivalent resolution

      • 1 bit quantization noise

      • Continuous reconstruction (useful feature for signal analysis)

    Input waveform

    Continuous reconstruction

    400ns sampled (cfr. FADC)

    16 MHz

    25 MHz

    Slight pulse height reduction but area (= charge) unchanged

    CryoDet workshop, LNGS

    Signals from lar

    Signals from LAr

    • LAr signal waveforms (from oscilloscope) digitized with Serial AD converter simulator

    • FIR comb filter applied to recover signal shape (16 sample width)

    • Quantization noise well within analogue noise level

    Input waveform

    Continuous reconstruction

    400ns sampling

    16 MHz

    25 MHz

    CryoDet workshop, LNGS

    Prototype board

    Prototype board

    • 16 channels

    • 16 MHz sampling rate

    • Data link compatible with ICARUS DAQ

    • Effective throughput 256 Mbit/s

    Charge sensitive preamplifiers

    Digital link

    4 x 4 channel serial AD converters

    CryoDet workshop, LNGS

    First signals from prototype

    First signals from prototype

    • Test pulse injected on on-board preamplifiers

    • Digitized signal recorded with ICARUS DAQ

    • Off-line signal reconstruction with FIR comb filter (16 sample width)

    Input waveform

    Continuous reconstruction

    400ns sampling

    16 MHz

    Zoom of gray shaded area

    High preamp. noise due to present board layout (analogue/digital interference)

    CryoDet workshop, LNGS



    • The ICARUS R&D on electronics for large LAr-TPC’s

      • Upgrade of the analogue front-end

        • VLSI-CMOS technology for high channel integration excluded by simple S/N requirements

        • Review of amplifier IC design could allow integrating more than two channel per chip

        • Use of HEMT at input could help improving S/N

    • Possible alternative solution

      • Development of a completely new cold amplifier (hybrid based on TOTEM structure with jFET matrix or HEMT) for better S/N

      • Major drawback: inaccessibility, component reliability, cost

  • Upgrade of Analogue-to-digital conversion

    • Serial-converter: promising alternative to Multiplexer + Flash ACD

    • Intrinsically simpler,more compact, cheaper

    • Comparable bandwidth and signal resolution

  • Review of the data link with digital buffers

    • Study the recent optical link development at LHC experiments to help defining a suitable solution for the LAr-TPC environment

  • CryoDet workshop, LNGS

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