Discussion cse 140l 3 rd november 2010
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DISCUSSION CSE 140L 3 rd November 2010. Vikram Murali. Things we will cover. Finite State Machines -- Mealy and Moore models. -- State Encoding. -- Simple Problem. VHDL Basics -- The Structure -- What we need !. FSM – Very Briefly.

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DISCUSSION CSE 140L 3 rd November 2010

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Discussion cse 140l 3 rd november 2010

DISCUSSION CSE 140L3rd November 2010

Vikram Murali


Things we will cover

Things we will cover

Finite State Machines

-- Mealy and Moore models.

-- State Encoding.

-- Simple Problem.

VHDL Basics

-- The Structure

-- What we need !


Fsm very briefly

FSM – Very Briefly

Mathematical abstraction used to design digital logic

Behavior model composed of a finite number of states, transitions between those states, and actions, similar to a flow graph.

Actually realising a problem statement or modelling it in digital logic.

Logic Flows when certain conditions are met.


Components

Components

States – Represent a state of the circuit (or the problem statement modelled). Characterised by the inputs that caused it to happen and the outputs it results in.

Inputs – Decide the flow between states.

Outputs.


Example

Example.

Outputs 1 when sequence is 1011 ! Seq. Detector


Mealy and moore models

Mealy and Moore Models


Another mealy machine

Another Mealy Machine


Difference

Difference.

Mealy model : Output depends on both the current state and the input.

Moore : It depends only on the current state.

Imagine : In a Moore machine, the output is associated with the state. In a mealy machine, the output is associated with the transitions.

Typically, Moore has more states, but is easier to implement. Mealy machines have less states, and also is fasterin clocked systems (the output occurs right away when the inputs are detected). Moore has to wait the clock cycle to transition to the next state before the output is changed. => Mealy can give rise to race conditions. !!


State encoding

State Encoding

States named as S0 , S1 … Sn are fine with us.

But implementation in Digital Logic ?

Each state must be encoded in 0s and 1s

Each bit has a certain state transition logic

-- We need to derive this to design our circuit

that implements our model/requirement

Eg : 8 states => 2^3 = 8 => 3 bits to encode.

111 DOWNTO 000


A quick problem traffic light cntrler

A Quick Problem. Traffic Light Cntrler !


Solution

Solution.

State Diagram.


State transition table

State transition table


Circuit after logic minimisation for a b and z

Circuit after logic minimisation for A+, B+ and Z.

A+

A

B+

B


Discussion cse 140l 3 rd november 2010

VHDL.

Major parts of a VHDL program

-- Entity Declaration

-- Architecture Body

-- Package Declaration

-- Package Body

-- Configuration

Synthesisable !


Look at the following program skeleton

“Look at the following program skeleton”


Discussion cse 140l 3 rd november 2010

Port name

Data-type

Mode


Individual syntaxes

Individual Syntaxes

ENTITY


Discussion cse 140l 3 rd november 2010

Example

ARCHITECTURE


What we want vhdl

What we want – VHDL.

States in VHDL

-- Building FSMs

-- State Transitions and Outputs


Thank you

THANK YOU !


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