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TMB and RAT Status Report

TMB and RAT Status Report. Jay Hauser University of California Los Angeles. TMB Hardware Since April Emu@OSU. Procured all FPGAs (Xilinx X2V4000) Got fixed Virtex-2 mezzanine layout from Kan I/O pads are grouped in pairs, each pair needs to use the same clock.

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TMB and RAT Status Report

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  1. TMB and RAT Status Report • Jay Hauser • University of California Los Angeles

  2. TMB Hardware Since April Emu@OSU • Procured all FPGAs (Xilinx X2V4000) • Got fixed Virtex-2 mezzanine layout from Kan • I/O pads are grouped in pairs, each pair needs to use the same clock. • Made 40 X2V4000 mezzanine cards • 2 remaining mezzanine card problems (there were 3 simple fixes) • Made 29 working sets (TMB-base, TMB-mezz, RAT) • 1 base board has a bad SCSI connector • 9 sets used for full-crate tests • No problems seen at FAST site • Procured all parts for full production (520 sets) • Still waiting for some hex switches and front-panel parts (due soon) • Full-crate tests done at OSU, no problems • May-June test beam problem found: • ALCT inputs through RAT did not work at all. • RPC inputs through RAT seemed okay (minor problems).

  3. RAT-to-TMB TTL Data Xmission • RAT gets everything (power, gnd, control signals) from TMB • Currently no connections to the common backplane RAT TMB NC Backplane

  4. RAT2003A Detail To TMB GND only To TMB and 3.3v, 1.8v power Mechanical Only  Spartan 2E FPGA for RPC ALCT LVDS-TTL converters RPC connectors ALCT SCSI connectors

  5. RAT-to-TMB Ground Problem • May-June test beam: • Only the bottom connector on backplane • 110 single-ended 80 MHz TTL signals from RAT to TMB. • Reference ground and current return on 6 pins. • “Typical” design used for all other modules in peripheral crate: • 1 GND per row of 5 pins, i.e. 25 GNDs per 125-pin connector • Ground reference close to every signal • Grounded to the backplane • It is not a DC current problem, it is an RF problem • 40 MHz noise • 80 MHz signals, edges with 1-2 ns rise times.

  6. Ground Issues, cont. • RPC signals seemed to work at May-June t.b. • They are buffered through FPGA close to connector • May have slightly better RF characteristics (N.B. no CRC available). • Also a problem: layout house for TMB used very thin ground and power planes • ½-oz thickness of copper • Usual thickness is 1-oz or 2-oz • Ground plane impedances therefore higher • Bench tests show very significant ground plane noise

  7. TMB Ground minus RAT Ground • No ALCT triggers • 300 mV P-P • 40 MHz noise depends on ALCT trigger rate: • 100 kHz ALCT • 600 mV P-P • 1 MHz ALCT • 700 mV P-P

  8. TMB-RAT Ground Details

  9. RAT-to-TMB Ground Problem • Bench investigations using CRC error checking of ALCT data: • Checks for any bit errors in ~800 bytes of data. • Rate of errors also seen to increase with ALCT trigger rate • Errors start when ALCT readout and triggering overlap in time • Reaches ~100% before 1 MHz. • Checks signal integrity through 8-bit DAQ path (out of 50 ALCT signals), i.e. many signals not checked. • UC FAST site investigations using CRC: • Typically 0.5-2.0% errors seen. • “New and improved” short backplane • 11 GNDs added, but on a different connector than TTL signals • No observed change in the rate of CRC errors.

  10. Test Beam Study of TMB-RAT Interface • CRC checks that every bit of ~800 bytes is transmitted correctly. • May-June test beam: • TMB backplane fed GND to RAT with only 6 pins. • ALCT data did not successfully go through at all. • Sept-Oct test beam: • TMB backplane had additional connector with 11 more GND pins. • ALCT errors were found only at high rates at the Sept-Oct test beam. • General observation that CRC errors increase with rate agrees with bench tests.

  11. Sept. 2004 Test Beam Study • High-rate CRC error test: • Went up to 3.4 million muons per spill before radiation alarms went off (ahem) • Otherwise, ALCT-RAT-TMB worked fine 74.5 Million ALCTs 15 CRC errors

  12. Conclusions on RAT-TMB Data Transmission Tests • Ground noise is quite large • Level of success of tests varies dramatically: • Absolutely no success at May-June beam test • Errors reproduced and understood with bench tests • Small rate of errors observed at UC FAST site • Very very small rate of errors observed at Sept beam test • Variable level of success not really surprising for a noise problem • Sitting on the edge of a serious problem • This situation is unacceptable for long-term CMS operation, we would like to eliminate this problem entirely

  13. Remedy • Make the grounding for RAT like any other board in the peripheral crate: • Add one ground pin on every row of RAT pins • Add backplane ground connections • Requires more total pins: • Replace 55-pin X3 and 125-pin X18 connectors by two 110-pin Type-A connectors • 40 more pins, all “C” column pins used for grounding • Also more robust alignment pins (noticed RAT alignment pins already broken before Sept beam test)

  14. Implications • Backplane layout needs modification • ~3 months, according to Alex • TMB and RAT board layouts need modification • Also ~3 months, according to our estimate • Includes thickening up the 1/2-oz ground and power planes and necessary changes to details of vias, thermal reliefs, etc. • Includes “cleaning up” the data pathway from RAT to TMB. • Revised “loop-back” backplane used for self-testing • will add proper RAT connection for production testing (previously RAT-TMB connectors inserted by hand, subject to bent pins) • More type-A connectors and backplane shrouds need to be ordered • Backplane pins have long lead-time, should be ordered immediately

  15. TMB/RAT Production Schedule • Mezzanine card production can begin next week • No problems seen with Virtex-II mezzanine card • Re-layout of RAT and TMB: • RAT: 2 weeks • TMB: ~10 weeks • Testing loop-back backplane: 1 week • Quick prototype cycle in February. • Production immediately after that. • Testing goes quickly, more than 4 boards per working day. • Deliveries of working TMB and RAT pairs: • 25% by April 30 (130 of 520 boards, including 10% spares) • 50% by June 30 (260 of 520 boards) • 75% by August 31 (390 of 520 boards) • 100% by October 31 (all 520 boards) • Boards will be shipped as soon as they are tested and acceptable space (not boxes) exists for them at CERN

  16. Happier Matters • Active pulsing of CFEB front ends • Active pulsing of test strips • DAQ error checking by CRC technique • New TMB counters

  17. DAQ Error Checking by CRC • CRC = Cyclic Redundancy Check • Special “checksum” (22 bits) added to end of data block to represent pattern of 1’s and 0’s sent • This checksum can be re-calculated from the 1’s and 0’s sent, then compared to the checksum received. • ALCT and TMB both create CRCs for their data. • TMB also checks ALCT CRC on the fly • TMB adds CRC-error bit to last ALCT trailer word. • TMB counts & stores in VME register the number of CRC errors from ALCT. • DDU now separates CRC errors coming from ALCT, CLCT/TMB. • CRC bench test: • Special ALCT firmware creates dummy buffer of 400 words and responds to external trigger • CRC can be checked at arbitrary rate with pulse generator

  18. TMB Counters • VME registers recently added for real-time counts of 23 various interesting things: • ALCTs • CLCTs • Matched LCTs • L1 Accepts • ALCT readout • CLCT readout • MPC accepts (muon 0, muon 1) • ALCT CRC errors • Etc. etc. • Very useful diagnostics at test beam

  19. Additional Slides Follow

  20. Active Pulsing of CFEB Front Ends • How it’s done: • All channels have capacitors with 4 levels of charge that can be preset (0,1,2,3) within Buckeye ASIC • “left half-strip” puts strip charges at ….,0,0,0,2,3,1,0,0,0… • “right half-strip” puts strip charges at …,0,0,0,1,3,2,0,0,0… • Single VME command to DMB pulses all channels simultaneously • Patterns give e.g. 6-layer CLCTs • First vary 40 MHz clock phase from TMB to comparators until patterns correctly found • Then patterns can be swept across entire chamber and checked • Advantages: • Finds optimum phase of 40 MHz clock to comparators • Checks all Buckeye, comparator, and CFEB-TMB Skewclear cable channels • Test takes a few minutes • No gas, HV, etc. needed

  21. Active Pulsing of Test Strips • How it’s done: • CCB provides 500ns gate to make the ALCT test strip pulses • Capacitive coupling between test strips and anode wire groups gives pulses on leading and trailing edges of 500ns pulse • All channels fire on leading edge • Hot wire mask on ALCT board  ALCT patterns • Like CFEB, vary 40 MHz receive and send phases until optimum data transmission from TMB to and from ALCT • Find optimum in 2D matrix of receive/send clock phases • Scan patterns across chamber to find bad AFEB/ALCT channels • Advantages: • Set up phases of 80 MHz clock TMB to and from ALCT with high reliability without HV, gas, or cosmic ray data • Check all AFEB, ALCT, and Skewclear channels through the system • What previously took days now takes minutes

  22. More on TMB and RAT Power

  23. TMB Ground minus RAT Ground • No ALCT triggers • 300 mV P-P • 40 MHz noise depends on ALCT trigger rate: • 100 kHz ALCT • 600 mV P-P • 1 MHz ALCT • 700 mV P-P

  24. Other Noise Measurements • RAT GND versus RAT +3.3v (okay) 100 mV/division • GND vs +3.3v • Clock off • GND vs +3.3v • Clock ON • ALCT 1 MHz • GND vs +3.3v • Clock ON

  25. Other Noise Measurements • TMB GND versus TMB +3.3v (okay) 100 mV/division • GND vs +3.3v • Clock off • GND vs +3.3v • Clock ON • ALCT 1 MHz • GND vs +3.3v • Clock ON

  26. Other Noise Measurements • TMB “logic 1” signal as seen at RAT, 2v per division • Big noise seen, as expected from GND(TMB) – GND(RAT) measurements • Logic 1 • Clock off • Logic 1 • Clock ON ! • Logic 1 • Clock ON & • ALCT 1 MHz

  27. LVTTL (from +3.3v) Logic Levels • Typical outputs 0.4v low, 2.4v high, transition ~1.5v • Worst case output supposed to be 0.8v low, 2.0v high • Measurements show violation of that

  28. TMB, RAT Power Supply Filtering Capacitor Design • TMB base board • Power sources for +3.3v and +1.8v: 2x100uF, 4x4.7uF, 1x1uF, 1x0.1uF • Power destinations: hundreds of 0.1 uF capacitors across board, typically several for each driver • Power sources for +3.3v and +1.5v for RAT: 1x100uF, 1x4.7uF, 1x1uF, 1x0.1uF • RAT board • 3x4.7uF, 12x0.1uF • Many 0.1 uF capacitors distributed across board, several for each driver • Virtex-II mezzanine board • 2x330uF, 10x47uF, ~20x0.1uF, ~40x0.022uF distributed according to Xilinx spec. • Connections to TMB base board with 56 ground pins, 19 +1.5v pins, 17 +3.3v pins • Comment: looks OK

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