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Registers & Counters

Registers & Counters. Mantıksal Tasarım – BBM231 M. Önder Efe onderefe@cs.hacettepe.edu.tr. Registers. Registers are clocked sequential circuits A register is a group of flip-flops Each flip-flop capable of storing one bit of information An n-bit register consists of n flip-flops

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Registers & Counters

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  1. Registers & Counters Mantıksal Tasarım – BBM231 M. Önder Efe onderefe@cs.hacettepe.edu.tr

  2. Registers • Registers are clocked sequential circuits • A register is a group of flip-flops • Each flip-flop capable of storing one bit of information • An n-bit register • consists of n flip-flops • capable of storing n bits of information • besides flip-flops, a register usually contains combinational logic to perform some simple tasks • In summary • flip-flops to hold information • combinational logic to control the state transition

  3. Counters • A counter is essentially a register that goes through a predetermined sequence of states • “Counting sequence” Register FF0 FF1 FFn-1 Combinational logic

  4. Uses of Registers and Counters • Registers are useful for storing and manipulating information • internal registers in microprocessors to manipulate data • Counters are extensively used in control logic • PC (program counter) in microprocessors

  5. Q0 D0 Q D C R Q1 D1 Q D C R Q2 D2 Q D C R Q3 D3 Q D C clock R clear 4-bit Register REG clear Q0 D0 Q1 D1 Q2 D2 Q3 D3 FD16CE 16 16 Q[15:0] D[15:0] CE C CLR

  6. VerilogCode of FD16CE • always @ (posedge C or posedge CLR) • begin • if (CLR) • Q <= 4’b0000; • else • begin • if (CE) • Q <= D; • end • end

  7. Q0 Q D D0 C R Q1 Q D D1 C R Q2 Q D D2 C R Q3 Q D D3 C R clock clear Register with Parallel Load Load

  8. clock 010…10 110…11 R1 load R2 010…10 Register Transfer 1/2 load n R2 R1 R2 R1 clock

  9. n-bit adder n n load Register Transfer 2/2 R2 R1 clock R1 R1 + R2

  10. SO SI Q Q Q Q D D D D C C C C clock Shift Registers • A register capable of shifting its content in one or both directions • Flip-flops in cascade serial output serial input • The current of n-bit shift register state can be transferred in n clock cycles

  11. clock shift control clk T1 T2 T3 T4 Serial Mode • A digital system is said to operate in serial mode when information is transferred and manipulated one bit a time. SO SI SO shift register A shift register B SI clock clk clk shiftcontrol

  12. Timing pulse Shift register A Shift register B initial value 1 0 1 1 0 0 1 0 After T3 After T4 1 0 1 1 1 0 1 1 clock shift control clk T1 T2 T3 T4 Serial Transfer B  A • Suppose we have two 4-bit shift registers After T1 After T2 A B clk clk shiftcontrol clock

  13. serial output SI SO clock shiftcontrol serial input SI SO Q D C Serial Addition • In digital computers, operations are usually executed in parallel, since it is faster • Serial mode is sometimes preferred since it requires less equipment shift register A FA a S b C C_in shift register B clear

  14. clock 00 10 00 00 SR-A SR-B C_in Example: Serial Addition • A and B are 2-bit shift registers shift control 01 01 14

  15. Universal Shift Register • Capabilities: • A “clear” control to set the register to 0. • A “clock” input • A “shift-right”control • A “shift-left” control • n input lines & a “parallel-load” control • n parallel output lines

  16. parallel outputs A2 A0 A3 A1 Q Q Q Q C C C C D D D D clear clk 41 MUX 41 MUX 41 MUX 41 MUX s1 s0 1 1 1 3 2 0 3 2 0 1 3 2 0 3 2 0 parallel inputs 4-Bit Universal Shift Register serial input for shift-left serial input for shift-right

  17. VerilogCode – v1 • // Behavioral description of a 4-bit universal shift register • // Fig. 6.7 and Table 6.3 • moduleShift_Register_4_beh ( // V2001, 2005 • outputreg [3: 0] A_par, // Registeroutput • input [3: 0] I_par, // Parallelinput • input s1, s0, // Select inputs • MSB_in, LSB_in, // Serialinputs • CLK, Clear_b// Clock and Clear • always @ ( posedge CLK, negedgeClear_b) // V2001, 2005 • if (Clear_b == 0) A_par <= 4’b0000; • else • case ({s1, s0}) • 2'b00: A_par <= A_par; // No change • 2'b01: A_par <= {MSB_in, A_par[3: 1]}; // Shift right • 2'b10: A_par <= {A_par[2: 0], LSB_in}; // Shift left • 2'b11: A_par <= I_par; // Parallel load of input • endcase • endmodule

  18. VerilogCode – v2 • // Behavioral description of a 4-bit universal shift register • // Fig. 6.7 and Table 6.3 • moduleShift_Register_4_beh ( // V2001, 2005 • outputreg [3: 0] A_par, // Registeroutput • input [3: 0] I_par, // Parallelinput • input s1, s0, // Select inputs • MSB_in, LSB_in, // Serialinputs • CLK, Clear_b// Clock and Clear • always @ ( posedge CLK, negedgeClear_b) // V2001, 2005 • if (Clear_b == 0) A_par <= 4’b0000; • else • case ({s1, s0}) • // 2'b00: A_par <= A_par; // No change • 2'b01: A_par <= {MSB_in, A_par [3: 1]}; // Shift right • 2'b10: A_par <= {A_par [2: 0], LSB_in}; // Shift left • 2'b11: A_par <= I_par; // Parallel load of input • endcase • endmodule

  19. Universal Shift Register

  20. Counters • registers that go through a prescribed sequence of states upon the application of input pulses • input pulses are usually clock pulses • Example: n-bit binary counter • count in binary from 0 to 2n-1 • Classification • Synchronous counters • flip-flops receive the same common clock as the pulse • Ripple counters • flip-flop output transition serves as the pulse to trigger other flip-flops

  21. Binary Ripple Counter 3-bit binary ripple counter • Idea: • to connect the output of one flip-flop to the C input of the next high-order flip-flop • We need “complementing” flip-flops • We can use T flip-flops to obtain complementing flip-flops or • JK flip-flops with its inputs are tied together or • D flip-flops with complement output connected to the D input.

  22. A0 A0 Q Q T D count count C C R R A1 A1 Q Q D T C C R R A2 A2 Q Q D T C C R R A3 logic-1 A3 Q Q T D C C R R clear clear 4-bit Binary Ripple Counter

  23. A0 Q T count C R A1 Q T C R A2 Q T C R logic-1 A3 Q T C R clear 4-bit Binary Ripple Counter

  24. Synchronous Counters • There is a common clock • that triggers all flip-flops simultaneously • If T = 0 or J = K = 0 the flip-flop does not change state. • If T = 1 or J = K = 1 the flip-flop does change state. • Design procedure is so simple • no need for going through sequential logic design process • A0 is always complemented • A1 is complemented when A0 = 1 • A2 is complemented when A0 = 1 and A1 = 1 • so on

  25. A0 Q J C Count_enable K A1 Q J C K A2 Q J C K A3 Q J C to next stage K clock 4-bit Binary Synchronous Counter Polarity of the clock is not essential

  26. Timing of Synchronous Counters clock A0 A1 A2 A3

  27. Timing of Ripple Counters clock A0 A1 A2 A3 27

  28. Up-Down Binary Counter • When counting downward • the least significant bit is always complemented (with each clock pulse) • A bit in any other position is complemented if all lower significant bits are equal to 0. • For example:0100 • Next state: • For example: 1100 • Next state:

  29. up A0 Q T down C A1 Q T C A2 Q T C clock C Up-Down Binary Counter • The circuit

  30. count load D0 A0 Q J C K D1 A1 Q J C K D2 A2 Q J C K carry output clock clear Binary Counter with Parallel Load

  31. Binary Counter with Parallel Load Function Table

  32. shift right T0 T1 T2 T3 Other Counters • Ring Counter • A ring counter is a circular shift register with only one flip-flop being set at any particular time, all others are cleared. initial value 1000 • Usage • Timing signals control the sequence of operations in a digital system

  33. clock T0 T1 T2 T3 Ring Counter • Sequence of timing signals

  34. 2-bit counter count Ring Counter • To generate 2n timing signals, • we need a shift register with ? flip-flops • or, we can construct the ring counter with a binary counter and a decoder T0 T1 T2 T3 • Cost: • 2 flip-flops • 2-to-4 line decoder • Cost in general case: • n flip-flops • n-to-2n line decoder • 2n n-input AND gates • n NOT gates 2x4 decoder

  35. X Y Z T Q Q Q Q D D D D C C C C X’ Y’ Z’ T’ clock Johnson Counter • A k-bit ring counter can generate k distinguishable states • The number of states can be doubled if the shift register is connected as a switch-tail ring counter

  36. sequence number Flip-flop outputs Output X Y Z T 1 0 0 1 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 0 1 1 0 0 1 0 0 1 2 3 4 5 6 7 8 Johnson Counter • Count sequence and required decoding S0 = X’T’ S1 = XY’ S2 = YZ’ S3 = ZT’ S4 = XT S5 = X’Y S6 = Y’Z S7 = Z’T

  37. S1 S2 S0 S3 S4 S5 S6 S7 X Y Z T Q Q Q Q D D D D C C C C clock Johnson Counter • Decoding circuit

  38. 1000 1100 1001 0100 1110 1010 0001 0101 0011 0111 1111 1011 0110 1101 Unused States in Counters • 4-bit Johnson counter 0000 0010

  39. 1000 1100 1001 1110 1010 0001 0101 0011 0111 1111 1011 0110 1101 Correction 0000 0010 0100

  40. Present State Next State X Y Z T X Y Z T 0 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 0 1 1 0 1 1 1 0 1 0 1 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 0 1 0 1 0 1 0 0 1 0 Johnson Counter

  41. K-Maps Y(t+1) = XY + XZ + XT’ X(t+1) = T’ Z(t+1) = Y T(t+1) = Z

  42. X Y Z T Q Q Q Q D D D D C C C C clock Unused States in Counters Y(t+1) = XY + XZ + XT’ X(t+1) = T’ Z(t+1) = Y T(t+1) = Z • Remedy DY = X(Y+Z+T’)

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