EE434 ASIC & Digital Systems

1. EE434ASIC & Digital Systems Jacob Murray School of EECS Washington State University jmurray@eecs.wsu.edu

2. Digital Design with VHDL Lecture 17

3. Synthesis Logic synthesis converts the HDL model to a structural netlist.

4. Synthesis Flow for Programmable Logic

5. Synthesis & Programmable Devices • Synthesis • Creating logic equations from the VHDL code • Fitting • Fit the logic into a programmable logic device • CPLDs • Logic is partitioned into logic blocks and signals are routed using the PIA • FPGAs • Logic is placed in the array of cells & signals are routed between those cells

6. Initialization and Reset A VHDL process with a sensitivity list synthesizes to clocked logic with a reset process (signal_1, signal_2) begin if (signal_2'eventand signal_2 = '0') then -- Insert initialization and reset statements. elsif (signal_1'event and signal_1 = '1') then -- Insert clocking statements. end if; end process;

7. Combinational Logic • A level-sensitive processhas a sensitivity list with signals that are not tested for event attributes. • Combinational logic uses a level sensitive process or a concurrent assignment statement. • Some synthesizers do not allow a signal inside a level-sensitive process unless the signal is in the sensitivity list. entity And_Bad is port (a, b: in BIT; c: out BIT); end And_Bad; architecture Synthesis_Bad of And_Bad is begin process (a) -- this should be process (a, b) begin c <= a and b; end process; end Synthesis_Bad;

8. Sequential Logic • No sensitivity list with a wait until statement • Sensitivity list and test for 'event plus a specific level • Any signal assigned in an edge-sensitive processstatement should be reset.

9. FSM Synthesis • Omit special synthesis directives • This will prevent any reassignment of states • Easiest but inefficient • Use directives (pragma) • Improved state assignment • Special state-machine compiler

10. Memory Synthesis • Random logic using flip-flops or latches • Inefficient in terms of area • Register files in datapaths • RAM standard components • RAM compiler

11. Messages while Synthesizing port (sel : in bit := ‘0’ ; ………..); warning : Default values on interface signals are not supported port (a : bit_vector; …….); warning : An index range must be specified for this data type signalmuxout, regout, add : bit_vector (7 downto 0); warning : name is reserved word

12. Synthesis Scripts • analyze -format vhdl -lib WORK { “and_g.vhd” “demux14.vhd” “demux_olc.vhd”………………. “sw_port.vhd” } • elaborate sw_port • write -format vhdl -hierarchy –output sw_port_gates.vhd" • write -format verilog -hierarchy –output sw_port_gates.v" • report_area > syn_sw_port_report_area.rpt • report_constraint -max_delay -verbose -all_violators > syn_sw_port_report_constraint_setup_all.rpt

13. Design Example entity arbiter is port ( clk : in std_logic; r1, r2, r3, r4 : in std_logic; grant_1, grant_2, grant_3, grant_4 : out std_logic; reset : in std_logic); end arbiter; architecture structural of arbiter is component grant port ( clk : in std_logic; r1, r2, r3, r4, reset : in std_logic; p12, p12b, p13, p13b, p14, p14b : in std_logic; p23, p23b, p24, p24b, p34, p34b : in std_logic; grant1, grant2, grant3, grant4 : out std_logic); end component; component p_matrix port ( clk : in std_logic; reset, grant1, grant2, grant3, grant4 : in std_logic; p12, p12b, p13, p13b, p14, p14b : out std_logic; p23, p23b, p24, p24b, p34, p34b : out std_logic); end component; ... end structural;

14. Synthesized Netlist entity grant is port( clk, r1, r2, r3, r4, reset, p12, p12b, p13, p13b, p14, p14b, p23, p23b , p24, p24b, p34, p34b : in std_logic; grant1, grant2, grant3, grant4 : out std_logic); end grant; architecture SYN_behaviour of grant is component SDFRPQ1 port( Q : out std_logic; CK, D, RB, SD, SE : in std_logic); end component; component INVD0 port( Z : out std_logic; A : in std_logic); end component; component NAN2M1D1 port( Z : out std_logic; A1, A2 : in std_logic); end component; component OA221D1 port( Z : out std_logic; A1, A2, B1, B2, C : in std_logic); end component;

15. Synthesized Netlist (Cont’d) signal n_6, n_8, n_19, n_21, n_32, n_34, n_45, n_47, n91, n92, n93, n94, n95, n96, n97, n98 : std_logic; begin grant4_reg : SDFRPQ1 port map( Q => grant4, CK => clk, D => n98, RB => n97, SD => n_47, SE => n_45); grant3_reg : SDFRPQ1 port map( Q => grant3, CK => clk, D => n96, RB => n97, SD => n_34, SE => n_32); grant2_reg : SDFRPQ1 port map( Q => grant2, CK => clk, D => n95, RB => n97, SD => n_21, SE => n_19); grant1_reg : SDFRPQ1 port map( Q => grant1, CK => clk, D => n94, RB => n97, SD => n_8, SE => n_6); ...

16. Area Reporting Library(s) Used: vst_n18_sc_tsm_c4_typ Number of ports: 10 Number of nets: 22 Number of cells: 2 Number of references: 2 Combinational area: 683.018066 Noncombinational area: 1333.516113 Total cell area: 2016.533936

17. Warm Up Lab

18. Memory Controller

19. Description • First a synchronous reset places the state machine in the idle state. When the memory buffer is not being accessed, the controller remains in the idle state. • If the bus_id is asserted as F3 (hex) while the controller is in idle, then the machine transitions to the decision state. (F3 is just an example; feel free to choose your bus id) • On the next clock cycle, the controller transitions to either read1 or write state, depending on the value of RW signal. • If the access is a read, the controller branches to the read portion of the state machine. A single-word read is indicated by the assertion of ready without the assertion of burst while in the read1 state. In this case, the controller returns to the idle state. • A burst read is indicated by the assertion of both ready and burst while in the read1 state. In this case the machine transitions through each of the read states, advancing on ready. OE (Output Enable) is asserted during each of the read cycles. Addr is incremented in successive read cycles following the first.

20. Description (Cont’d) • If the access is a write, it can only be single-word write. • Therefore, after determining that the access is a write in the decision state, the controller branches to the write portion of the state machine. • It asserts WE to the memory buffer, waits for the ready signal from the bus, and then returns directly to the idle state.

22. State Machine Translate the state flow diagram to a series of case-when statements. casepresent_stateis when idle => oe <= ‘0’;……. if (bus_id = “11110011”) then next_state <= decision; else next_state <= idle; end if;

23. State Machine (cont’d.): Burst Read when read1 => mention the outputs if (ready = ‘0’) then next_state <= read1; elsif (burst=‘0’) then next_state <= idle; else next_state <= read2; end if;