Asic 120 digital systems and standard cell asic design
Download
1 / 90

ASIC 120: Digital Systems and Standard-Cell ASIC Design - PowerPoint PPT Presentation


  • 160 Views
  • Uploaded on

ASIC 120: Digital Systems and Standard-Cell ASIC Design. Tutorial 1: Introduction to Digital Circuits January 25, 2006. Outline. Digital Systems Digital Design and its relation to ASICs Combinational Logic NOT, AND, OR, XOR, NAND, etc. mux, half-adder, full-adder Sequential Logic

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' ASIC 120: Digital Systems and Standard-Cell ASIC Design' - yaron


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
Asic 120 digital systems and standard cell asic design

ASIC 120: Digital Systems and Standard-Cell ASIC Design

Tutorial 1: Introduction to Digital Circuits

January 25, 2006


Outline
Outline

  • Digital Systems

  • Digital Design and its relation to ASICs

  • Combinational Logic

    • NOT, AND, OR, XOR, NAND, etc.

    • mux, half-adder, full-adder

  • Sequential Logic

    • flip-flop/register, shift register, counter


Digital systems
Digital Systems

  • Analog vs. Digital

    • continuously varying vs. discrete

    • imprecise vs. precise

    • 0..1 vs. 0 or 1

  • Digital systems excel at…

    • repetitive calculations

    • large amounts of data

    • reproducible results


Digital systems1
Digital Systems

  • Implemented in integrated circuits (ICs) mounted on a printed circuit board (PCB)




Components of a digital system
Components of a Digital System

  • Printed circuit board (PCB)

  • Embedded software

    • microprocessor

    • microcontroller

    • digital signal processor (DSP)

  • ASIC

  • Programmable Logic Device (PLD)

    • FPGA, etc.


Asics
ASICs

  • Application Specific Integrated Circuit

    • from a user perspective, implies integrated circuit with a specific application

    • from a design perspective, implies any integrated circuit

  • Since we are designers, ASICs include

    • SRAMs

    • phase locked loops (PLLs)

    • microprocessors

    • analog-to-digital converters

    • FPGAs

    • etc.


Consider an asic
Consider an ASIC

  • Physically comprised of

    • Package

    • Pins

    • Silicon wafer

      • metal interconnect layers

      • insulating layers

      • vias

      • at the bottom, transistors resting on a silicon substrate



Consider an asic side view
Consider an ASIC: Side View

Source: Figure 3-11 from ECE 438 textbook (Rabaey, Jan M., Anantha Chandrakasan, Borivoje Nikolić, “Digital Integrated Circuits: A Design Perspective,” 2nd Edition; Pearson Education: New Jersey, 2003.)


Consider an asic substrate
Consider an ASIC: Substrate

Source: Figure 3-13 from ECE 438 textbook (Rabaey et al., “Digital Integrated Circuits,” 2nd Edition)


Consider an asic1
Consider an ASIC

  • Conceptually

    • System

    • Module

    • Gate

    • Circuit

    • Device

Source: Figure 1-6 from ECE 438 textbook (Rabaey et al., “Digital Integrated Circuits,” 2nd Edition)


Fpgas
FPGAs

  • Field Programmable Gate Array

    • part of the Complex Programmable Logic Device (CPLD) family of PLDs

    • essentially reprogrammable hardware

  • FPGAs can be very small or very big

    • clock rates over 1 GHz

    • implement multiple 32-bit processors


Components of an fpga
Components of an FPGA

  • Logic Elements (LEs)

  • Routing

  • Input/Output logic

  • Extra features

    • clocking

    • memory

    • memory interfaces

    • multipliers


The logic element
The Logic Element

  • Two main parts

    • Look-Up Table (LUT) for combinational logic

    • Flip Flop (FF) for sequential logic (memory)




Digital asic fpga design flow
Digital ASIC/FPGA Design Flow

  • Dependent on target environment, process, resources available, etc.

  • Generic flow:

    • System architecture

    • Register Transfer Level (RTL)

      • high level, synthesizable, optimized

      • functional simulation, timing simulation

    • Synthesis

      • more simulation

    • Manufacturing

      • testing


Register transfer level rtl
Register Transfer Level (RTL)

  • This is where we start

    • schematic

    • hardware description languages (VHDL, etc.)


Combinational and sequential logic
Combinational and Sequential Logic

  • We can break a digital system into two types of logic

  • Combinational

    • computation happens in a linear fashion

  • Sequential

    • computation involves a feedback loop (memory)


Rtl and combinational sequential logic
RTL and Combinational/Sequential Logic

Sequential

Feedback

Data

Out

Data

In

Register

Register

Register

Cloud

of Logic

Cloud

of Logic

Clock

Combinational


Combinational logic not
Combinational Logic: NOT

Truth Table

Input

Output

Boolean algebra expression: X = A


Combinational logic and
Combinational Logic: AND

Boolean algebra expressions: X = A  B

X = AB


Combinational logic or
Combinational Logic: OR

Boolean algebra expression: X = A + B


Combinational logic xor
Combinational Logic: XOR

Boolean algebra expression: X = A  B


Combinational logic nand
Combinational Logic: NAND

Boolean algebra expressions: X = A  B

X = AB




Combinational logic nor xnor
Combinational Logic: NOR, XNOR

X = A + B

X = A  B



Combinational logic mux multiplexer
Combinational Logic: MUX(multiplexer)

X = AC + BC


Half adder
Half Adder

S = A  B

C = AB


Full adder
Full Adder

S = A  B  Ci

Co = AB + Ci(A  B)



Full adder application 8 bit ripple carry adder

A B

A B

A B

A B

A B

A B

A B

A B

Ci Co

Ci Co

Ci Co

Ci Co

Ci Co

Ci Co

Ci Co

Ci Co

S

S

S

S

S

S

S

S

Full Adder Application: 8-BitRipple-Carry Adder

  • Constructed by connecting 8 full adders together

A0

B0

A1

B1

A2

B2

A3

B3

A4

B4

A5

B5

A6

B6

A7

B7

0

Carry

Out

S0

S1

S2

S3

S4

S5

S6

S7


What i ve skipped
What I’ve Skipped

  • Gates with more than two inputs

  • Karnaugh maps

  • Quine-McCluskey method

  • Binary arithmetic, base conversions

  • Practical digital circuits have more than 0s and 1s

  • Transmission gates, tri-state buffers




Basic feedback element sr latch1

Simplified truth table:

Basic Feedback Element: SR Latch


Basic feedback element sr latch2
Basic Feedback Element: SR Latch

0

0

1

0

(Hold State)


Basic feedback element sr latch3
Basic Feedback Element: SR Latch

0

0

1

0

1

0

(Hold State)


Basic feedback element sr latch4
Basic Feedback Element: SR Latch

0

1

0

0

(Hold State)


Basic feedback element sr latch5
Basic Feedback Element: SR Latch

0

1

0

1

0

0

(Hold State)



Basic feedback element sr latch7
Basic Feedback Element: SR Latch

0

0

1

0

1

1

(Set State)


Basic feedback element sr latch8
Basic Feedback Element: SR Latch

0

0

1

0

0

1

(Set State)


Basic feedback element sr latch9
Basic Feedback Element: SR Latch

0

0

0

0

0

1

(Set State)


Basic feedback element sr latch10
Basic Feedback Element: SR Latch

0

1

0

0

0

1

(Set State)


Basic feedback element sr latch11
Basic Feedback Element: SR Latch

0

1

0

1

0

1

(Set State)


Basic feedback element sr latch12
Basic Feedback Element: SR Latch

1

0

1

1

(Invalid State)


Basic feedback element sr latch13
Basic Feedback Element: SR Latch

1

0

1

0

1

1

(Invalid State)


Basic feedback element sr latch14
Basic Feedback Element: SR Latch

1

0

1

0

0

1

(Invalid State)


Basic feedback element sr latch15
Basic Feedback Element: SR Latch

1

0

0

0

0

1

(Invalid State)


Basic feedback element sr latch16
Basic Feedback Element: SR Latch

  • Q and Q are supposed to have opposite (“complementary”) values

    • i.e., Q = Q

  • In the invalid state (S = 1, R = 1) Q ≠ Q

    • should be avoided



D flip flop or register1
D Flip-Flop or Register

  • Clock input controls when data output takes value of data input

    • triggered on either rising or falling edge of clock


Latches vs flip flops
Latches vs. Flip-Flops

  • Latches

    • no clock input

    • data output changes in response to data input

    • level-sensitive

  • Flip-Flops

    • has clock input

    • data output changes in response to data input on rising or falling clock edge

    • edge-sensitive


Synchronous vs asynchronous
Synchronous vs. Asynchronous

  • Synchronous

    • circuit operation governed by a clock

    • currently more popular and practical

    • flip-flops

  • Asynchronous

    • circuit operation independent of a clock

    • potentially faster than synchronous

    • lower power consumption

    • difficult to design

    • latches


Sequential constructs
Sequential Constructs

  • Shift registers

  • Counters

  • State Machines (next tutorial)


Shift register

D Q

D Q

D Q

D Q

DFF

DFF

DFF

DFF

Shift Register

  • Consider a series of D flip-flops (DFFs) connected in series, as a 4-bit shift register

Data

Out

Data

In

Clk


Shift register1

D Q

D Q

D Q

D Q

DFF

DFF

DFF

DFF

Shift Register

0

0

0

0

0

Data

Out

Data

In

0

Clk


Shift register2

D Q

D Q

D Q

D Q

DFF

DFF

DFF

DFF

Shift Register

0

0

1

0

0

Data

Out

Data

In

0

Clk


Shift register3

D Q

D Q

D Q

D Q

DFF

DFF

DFF

DFF

Shift Register

0

0

1

1

0

Data

Out

Data

In

(1)

Clk


Shift register4

D Q

D Q

D Q

D Q

DFF

DFF

DFF

DFF

Shift Register

0

0

0

1

0

Data

Out

Data

In

(0)

Clk


Shift register5

D Q

D Q

D Q

D Q

DFF

DFF

DFF

DFF

Shift Register

0

0

0

0

1

Data

Out

Data

In

(1)

Clk


Shift register6

D Q

D Q

D Q

D Q

DFF

DFF

DFF

DFF

Shift Register

1

0

0

0

0

Data

Out

Data

In

(1)

Clk


Shift register7

D Q

D Q

D Q

D Q

DFF

DFF

DFF

DFF

Shift Register

0

1

0

0

0

Data

Out

Data

In

(1)

Clk


Counters ring counter

D Q

D Q

D Q

D Q

DFF

DFF

DFF

DFF

S C

S C

S C

S C

Counters: Ring Counter

  • Connect shift register output to input

  • Add set and clear functionality to DFFs

Clk

Init


Counters ring counter1

D Q

D Q

D Q

D Q

DFF

DFF

DFF

DFF

S C

S C

S C

S C

Counters: Ring Counter

0

0

0

1

0

Clk

1

Init


Counters ring counter2

D Q

D Q

D Q

D Q

DFF

DFF

DFF

DFF

S C

S C

S C

S C

Counters: Ring Counter

0

0

0

1

0

Clk

0

Init


Counters ring counter3

D Q

D Q

D Q

D Q

DFF

DFF

DFF

DFF

S C

S C

S C

S C

Counters: Ring Counter

0

0

0

0

1

(1)

Clk

0

Init


Counters ring counter4

D Q

D Q

D Q

D Q

DFF

DFF

DFF

DFF

S C

S C

S C

S C

Counters: Ring Counter

1

0

0

0

0

(1)

Clk

0

Init


Counters ring counter5

D Q

D Q

D Q

D Q

DFF

DFF

DFF

DFF

S C

S C

S C

S C

Counters: Ring Counter

0

1

1

0

0

(1)

Clk

0

Init


Counters ring counter6

D Q

D Q

D Q

D Q

DFF

DFF

DFF

DFF

S C

S C

S C

S C

Counters: Ring Counter

  • Each DFF output is a digit in a binary number

  • Sequence was: 1000 (8)

    0100 (4)

    0010 (2)

    0001 (1)

    1000 (8)

0

0

0

1

0

(1)

Clk

0

Init


T flip flop
T Flip-Flop

  • Clock is the only input

  • Output inverts on rising edge of the clock (or “toggle”) input


Counters binary counter

Q

Q

Q

Q

T

T

T

T

Counters: Binary Counter

  • Implemented using series of T flip-flops

  • Counts 0000, 0001, 0010, 0011, etc.

Clk


Counters binary counter1

Q

Q

Q

Q

T

T

T

T

Counters: Binary Counter

0

0

0

0

Clk


Counters binary counter2

Q

Q

Q

Q

T

T

T

T

Counters: Binary Counter

0

0

1

0

(1)

Clk


Counters binary counter3

Q

Q

Q

Q

T

T

T

T

Counters: Binary Counter

0

0

0

1

(1)

Clk


Counters binary counter4

Q

Q

Q

Q

T

T

T

T

Counters: Binary Counter

0

0

1

1

(1)

Clk


Counters binary counter5

Q

Q

Q

Q

T

T

T

T

Counters: Binary Counter

1

0

0

0

(1)

Clk


Counters binary counter6
Counters: Binary Counter

and so on…

1

0

1

0

Q

Q

Q

Q

(1)

Clk

T

T

T

T


State machines
State Machines

  • Useful abstract constructs for more complex sequential logic

  • More on these next time


What i ve skipped1
What I’ve Skipped

  • Other flip-flops (RS, JK)

  • Many other interesting sequential circuits (barrel shifters, gray counters, etc.)


Hardware description languages hdls
Hardware Description Languages (HDLs)

  • HDL describes in text a digital circuit

  • Examples

    • VHDL (we will look at this next time)

    • Verilog

    • AHDL

    • JHDL


Hardware description languages hdls1
Hardware Description Languages (HDLs)

  • schematics are useful for…

    • drawing high level diagrams

    • manually working out simple pieces of logic

  • HDLs are useful for…

    • describing complex digital systems

  • HDLs are not...

    • software programming languages (C, Java, assembly, etc.)


Summary
Summary

  • Digital Systems

  • Digital Design and its relation to ASICs

  • Combinational Logic

    • NOT, AND, OR, XOR, NAND, etc.

    • mux, half-adder, full-adder

  • Sequential Logic

    • flip-flop/register, shift register, counter


Next tutorial
Next Tutorial

  • State machines

  • Tutorial 1 in VHDL

  • Digital Design Thought Process

    • VHDL is not a programming language like C or Java

    • hardware entities represented using text


Uw asic design team
UW ASIC Design Team

  • www.asic.uwaterloo.ca

  • Reference material

    • Bryce Leung’s tutorials (UW ASIC website)

    • Michael Goldsmith’s tutorials (UW ASIC website)

    • ECE 223, 427, 438 course notes & textbooks

  • My contact info:

    Jeff Wentworth, [email protected]


ad