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CSC Muon Trigger On Detector Components

CSC Muon Trigger On Detector Components. B. Paul Padley Rice University June, 2002. CMS Endcap Muon System. 3 or 4 stations Each CSC chamber has six planes: Radial cathode strips for precision muon position and bend direction measurement

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CSC Muon Trigger On Detector Components

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  1. CSC Muon Trigger On Detector Components B. Paul Padley Rice University June, 2002

  2. CMS Endcap Muon System • 3 or 4 stations • Each CSC chamber has six planes: • Radial cathode strips for precision muon position and bend direction measurement • Anode wires for timing (bunch ID) and non-bend position measurement • There is also a RPC system overlapping the CSC’s to provide a redundant trigger

  3.  CSC Muon Triggering • Trigger primitives are wire and strip segments • Wires give 25ns bunch crossing • Strips give precision  information • Link trigger primitives into tracks • Assign pT, , and  • Send highest qualitytracks to Global L1

  4. Trigger requirements • Cathode LCT • Identify cathode track segment. Pt trigger based on angle of LCT • For Pt threshold of 20-40 GeV requires Dp/p < 30% (in order to limit single muon trigger rate in Level-1 to a few KHz) • Track hits must be located to within ½ strip width in each chamber layer • Anode LCT • Form anode track segment. • Tag bunch crossing of track segment with > 92 % efficiency per chamber

  5. EMU “Trigger” Cards • Anode LCT Card (ALCT) • Sits on Chamber • Receives Anode Front End Board discriminator signals • Finds eta coordinate of two best track stubs and quality • Sends to Trigger Motherboard • Trigger Motherboard (TMB) • Receives ALCT info • Receives Cathode Front End Board discriminator Signals • Finds location, bend angle and quality of two best cathode track stubs • Correlates Anode and Cathode LCT’s • Sends to Port Card (MPC)

  6. EMU “Trigger” Cards Cont’d • EMU Clock and Control Board (CCB) • Receives Clock and Control signals (such as L1accept, reset…) from Trigger Timing and Control system • Redistributes these signals on the custom backplane. • RPC Interface Module (RIM) • Transition module that receives RPC trigger information • Could be used in TMB to eliminate ghosts (if they are a problem).

  7. Trig Motherboard Clock Control Board DAQ Motherboard C C B D M B T M B D M B T M B D M B T M B D M B T M B D M B T M B M P C T M B D M B T M B D M B T M B D M B T M B D M B C O N T R O L L E R Peripheral Crate on iron disk 1 of 5 1 of 5 Cathode Front-end Board CFEB CFEB CFEB CFEB CFEB 1 of 2 1 of 24 ALCT LVDB Anode LCT Board Anode Front-end Board CSC Endcap Muon Trigger Primitive Generation Trigger-Timing-Control Optical link Muon Sector Receiver Lev-1 Trigger In underground counting room On detector

  8. C C B D M B T M B D M B T M B D M B T M B D M B T M B D M B T M B M P C T M B D M B T M B D M B T M B D M B T M B D M B C O N T R O L L E R Peripheral Crate There are 48 peripheral crates in the Endcap Muon system Only “on detector” “Trigger” board is the Muon Port Card (MPC) It accepts ALCT/CLCT pairs from each TMB Selects the best 3 and sends to counting room.

  9. CSC Sectors Data Mapping

  10. CSC Muon Trigger Scheme 3-D Track-Finding and Measurement On-Chamber Trigger Primitives Muon Port Card(Rice) Trigger Motherboard(UCLA) SectorReceiver/ Processor(U. Florida) Strip FE cards LCT OPTICAL FE SP SR/SP MPC LCT TMB 3 / port card FE 2 / chamber 3 / sector Wire LCT card Wire FE cards In counting house RIM CSC Muon Sorter(Rice) RPC Interface Module RPC DT 4 4 4 Combination of all 3 Muon Systems Global L1 Global  Trigger 4

  11. Responsibilities USCMS Endcap Muon USCMS Trigger/DAQ 3.1.1 OSU Cathode LCT/ Motherboard/ RPC Port Card Sector Receiver Sector Processor Cathode Front-End OPTICAL LCT SR/SP Florida 3.1.1.17 CFE MPC TMB AFE Anode LCT Anode Front-End CSC Muon Sorter Rice 3.1.1.15 RPC in. Rice 3.1.1.1 CMU RPC DT Rice /UCLA UCLA Global  Trigger Global L1 Vienna Also: 3.1.1.7 Backplanes - Florida 3.1.1.8-11 controllers, crates, power supplies, cables Clock & Control1 Clock & Control2 3.1.1.5 Rice

  12. Current Project Status • Trigger primitives are formally part of Endcap Muon project • ALCT • 384 channel version, in production • 672 and 288 channel versions – pre-production prototypes being evaluated • CLCT/TMB – 17 prototypes made – 3 debugged and being evaluated • First Track Finder system (TRIDAS) prototyped successfully in ‘00 • Also, trigger part of CMS OO simulation package was developed • Some hardware modifications were desired: • Decrease latency • Implement DAQ diagnostic readout • Currently Building 2nd prototypes of system

  13. Technical Issues Addressed with Second Prototypes • Level 1 trigger latency • Front-end buffer size is limited (tracking, pre-radiators) • Track Finder must deliver muons to GMT by 79 crossings (1975 ns) after muon collision • Prototype 1 (including trigger primitive electronics) was too slow – some surprises were encountered, e.g. Channel-Link latency about 100 ns ( x5 places used) • How to reach requirement is being incorporated in new design: • Optimize data transfer protocols between boards • Decrease some bit counts • Faster FPGA chips (often 80 MHz versus 40 MHz) • Improved FPGA algorithms

  14. Optical Link Radiation Tests • Three serializers: up to 270 kRad TID.No permanent damage or SEU • Two Finisar optical modules: No errors up to 70 kRad. • Failed at ~70kRad(well above~10 kRad TIDinner CSCdose for10 years) • -- Rice

  15. Muon Port Card Prototype 1 VME Interface Optical links Main FPGA on Daughter Card

  16. New MPC Design (Rice) 9U x 400 MM BOARD VME J1 CONNECTOR VME INTERFACE UCLA MEZZANINE CARD (XCV600E) CCB CCB INTERFACE SORTING LOGIC INPUT ANDOUTPUT FIFO CCB TMB_1 OPTO SER TMB_2 CUSTOM PERIPHERAL BACKPLANE 3 OPTICAL CABLES TO SECTOR PROCESSOR TMB_3 OPTO SER TMB_4 TMB_5 TMB_6 OPTO SER TMB_7 FINISAR FTRJ-8519-1-2.5 OPTICAL TRANSCEIVERS TMB_8 TLK2501 SERIALIZERS FPGA TMB_9 SN74GTLP18612 GTLP TRANSCEIVERS

  17. New Peripheral Backplane Bit 3 VME/PCI interface 3U VME A24D16 VME Display Custom Backplane

  18. New Port Card Breadboard area (always prudent) • Board is partially stuffed • We are adding components and then testing, iteratively • VME • JTAG • Input/output FIFO’s • Sorting Logic TLK2501 (1 of 3) VME connector Finisar optical transceiver (1 of 3) Custom backplane connector Mezzanine card with PLD (PLD is on other side)

  19. Personnel • Professors • Jay Hauser (UCLA), Paul Padley (Rice) • Postdocs • Martin Von der Mey (UCLA), TBA (Rice) • Students • Greg Pawloski (Rice) • Engineers • JK (UCLA), Mike Matveev (Rice), Ted Nussbaum (Rice)

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