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DT DAQ status and plans

DT DAQ status and plans. Cristina Fernández Bedoya , Ignacio Redondo Fernández. Intro/Outline. Present status is sound Permanently blocked channels 0-1ROB (down from 1) Downtime: 0 % (down from 1%) News Suppression of TS debug data Automatic TTSResync enabled Plans: Alarm Automation

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DT DAQ status and plans

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  1. DT DAQ status and plans Cristina Fernández Bedoya , Ignacio Redondo Fernández Ignacio Redondo CIEMAT

  2. Intro/Outline • Present status is sound • Permanently blocked channels 0-1ROB (down from 1) • Downtime: 0 % (down from 1%) • News • Suppression of TS debug data • Automatic TTSResync enabled • Plans: • Alarm Automation • Analysis of TestPulse runs taken • 904 teststand Ignacio Redondo CIEMAT

  3. Trigger “zero”-supression Cristina,Luigi,Gianni • TS data (20 bxs) only readout if trigger primitive present in the sector. • Otherwise send a 32 bit word. • Event size of emtpy event reduced by 6 from 1176 bytes/FED to 192 bytes/FED Events Ignacio Redondo CIEMAT Bytes

  4. Enables the switch to <10 DDU system • Required to beaf-up spares pool • Symmetric configuration (5 DDU) • External wheels configuration (7 DUU: 2,1,1,1,2) • How and when to be decided: • Probably during Christmas stop after Heavy Ion run. Ignacio Redondo CIEMAT

  5. Automatic resync enabled • Automatic resync enabled since August 26 • At present, DDU goes into OOS if more than 15 ROBs (2.5 Minicrates) are blocked (programmable). Already implemented in April. • DDU OOS is answered automatically by a resync from cDAQ • Being monitored: • 83 times, • 5 out of access • DT DAQ has disappeared from downtime reports (0.8 % => 0 %) Downtime before 08/26/2010 Ignacio Redondo CIEMAT

  6. DAQ Alarm Automation • DAQ alarm automation status: • Blocked channels above threshod =>TTSResync • SC crate off =>PVSS alarm to DCS shifter (SMS?)  • In general, only catched by expert look at DQM/DCS dashboard • DDU input channel blocked =>VME command? SMS? (or GOLROS not working)  • QPLL unlocks  => Need to know the clock status • FPGA not programmed =>  TTS signal? (most frequent SEU) VME command? • VME access problem =>Probably will have to power (now reported in the config phase) cycle manually, SMS PVSS alarm? • As luminosity increases we will start to be sensitive to SEU failures at the ROS that are rare now Ignacio Redondo CIEMAT

  7. Error Report to cDAQ Ignacio Redondo CIEMAT In any of the errors in the previous list, as a first step, the central shifter should get an alarm/warning and call the DT field manager.  Communications channels where to implement these alarms in our FM/DAQ xdaq are already in place We should be able to mask this alarms to cope with persistent errors.

  8. Firmware upgrades • By the end of the year in order to improve various aspects we plan to upgrade: • DDU firmware • Internal mapping of the number of ROS errors forOut-Of-Synch. • ROS firmware • Better event size monitoring.   • Reduce GOL power on/off cycles  • Possibility to remap TTSHardReset (now eq. to TTSResync) to FPGA reloading  • Improve ROS start-up procedure • All this things are still under development, hopefully all of them are doable. Vincenzo/Cristina Ignacio Redondo CIEMAT

  9. MiniDAQ Test Pulse Checked in the Online DQM various MiniDAQ TP runs taken aprox once/month in 2010: • Things checked: • - data integrity, • - event size, • - occupancies, • - TP time position, • - TP L1A BXid, • - noisy cells • Some conclusions: • -Not all known read-out errors appear in these runs, but most of them (the sample is quite representative) • -All known FE (FEB, SLs, etc) errors appear in these runs • -Noisy cells in TP have a very low noise frequency (<500 Hz) and do not correspond with the noisy cells seen with HV on • -Some trigger problems are also visible when reading with DCC Cristina Ignacio Redondo CIEMAT

  10. Some anomalous behaviours: -Some TDC fatal errors in March and April runs that were probably due to a wrong configuration (solved afterwards). -Two chambers in which the TP is largely shifted (and not related with any other problem). Looks also like a configuration problem (never happened afterwards) Run 130036 YB+1 S10 MB2 BAD, peak in 1250 TDC counts Run 132842 YB+1 S10 MB2 OK, peak in 680 TDC counts Ignacio Redondo CIEMAT

  11. TP error Summary • One thing to remark is that this year we have 3 FEB death. • Last time such problems have been seen: • January 2008: YB+1 S9 MB3 SL1 FEB 13 (short in VCC HV discharges) • January 2008: YB-1 S8 MB4 SL1 FEB 20 (short in VDD capacitor) • Test Pulse trainining during next Oncall Training? • Offline shifter please check known problem list/browser (https://twiki.cern.ch/twiki/bin/view/CMS/DTshiftFAQ2010x08x19)before submitting report to elog. Cristina Ignacio Redondo CIEMAT

  12. RO test stand in 904 Cristina,Vincenzo,Ignacio “Good” LHC Clock TTC (BG-O commands) DDU: DDU prototype CAEN VME bridge TTCvi, TTCex SC: Linco Tim 1 ROS Able to test ROS-DDU link (GOL) and debug DDU board. Ignacio Redondo CIEMAT

  13. RO test stand in 904 Cristina,Vincenzo,Ignacio “Micro”-crate (CCB+ROB) installed by Cristina. Provides Minicrate data Labview linco driver nearly ready, Will enable to replicate Madrid ROS tests. Decoupled DDU and ROS control Ready to install local DT DAQ software Ignacio Redondo CIEMAT

  14. More Ignacio Redondo CIEMAT

  15. Testpulses runs are not suited to make a thorough study of the local trigger chain due to Superlayer shifts. In particular, MB4s (2 cells shift) will never give HH triggers. Still, some “larger” problems can be spotted: Empty (DTTF YB-2 S4 MB4 masked) Cristina Ignacio Redondo CIEMAT

  16. DDU trigger data wrong, too many pre-triggering Ignacio Redondo CIEMAT

  17. DDU trigger data OK but DCC sees only HL and 1 bx later Ignacio Redondo CIEMAT

  18. How these plots should look like: Ignacio Redondo CIEMAT

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