Ese370 circuit level modeling design and optimization for digital systems
This presentation is the property of its rightful owner.
Sponsored Links
1 / 38

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems PowerPoint PPT Presentation


  • 77 Views
  • Uploaded on
  • Presentation posted in: General

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Day 19: October 22, 2010 Pass Transistor Logic. Today. Pass Transistor Logic Muxes Performance Composition Logic Tristates. Behavior. O=S*A + S*/B. S. A. B. Delay. Assume R 0 /2 drive 10C 0 load

Download Presentation

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Ese370 circuit level modeling design and optimization for digital systems

ESE370:Circuit-Level Modeling, Design, and Optimization for Digital Systems

Day 19: October 22, 2010

Pass Transistor Logic


Today

Today

  • Pass Transistor Logic

    • Muxes

    • Performance

    • Composition

    • Logic

    • Tristates


Behavior

Behavior

  • O=S*A + S*/B

S

A

B


Delay

Delay

  • Assume R0/2 drive

  • 10C0 load

  • What else need to know?

    • Cdiff=CSB or CDB

    • Assume Cdiff≈Cgate

5

2

5


Capacitances

Day 10

Capacitances

  • GS, GB, GD, SB, DB, SD


Contact capacitance

Day 10

Contact Capacitance

  • n+ contacts are formed by doping = diffusion

  • Depletion under contact

    • Contact-Body capacitance

  • Depletion around perimeter of contact

    • Also contact-Body capacitance


Contact diffusion capacitance

Day 10

Contact/Diffusion Capacitance

  • Cj – diffusion depletion

  • Cjsw – sidewall capacitance

  • LS – length of diffusion

LS


Delay1

Delay

5

2

5


Delay2

Delay


Cmos equivalent

CMOS Equivalent


Cmos delay

CMOS Delay

  • O=S*A + S*/B


What s different

What’s different?

  • What’s different about the output?


Output ok

Output ok?

  • Is the output usable?


Cmos dc transfer function

CMOS DC Transfer Function


After cmos inverter

After CMOS Inverter


What does this do

What does this do?


Cascade functional

Cascade Functional?


Voltage drop

Voltage Drop

  • Voltage drop across any number of series transistors is one Vth

  • Think about two series transistors as one transistor of twice the length


Pinch off

Day 9

Pinch Off

  • When voltage drops below VT, drops out of inversion

    • Occurs when: VGS-VDS< VT

  • Conclusion:

    • current cannot increase with VDS once VDS> VGS-VT

    • current must adjust so that VDS= VGS-VT

    • If current dropped to zero, then would invert and conduct again…


Performance

Performance?

  • Assume R0/2 drive

  • 10C0 load

  • Cdiff=Cgate

5

2

5


What does this do1

What does this do?

A

B


Performance1

Performance

  • R0/2 drive

  • 10C0 load

5

2

5


Performance2

Performance

  • R0/2 drive

  • 10C0 load


Not isolating

Not Isolating

  • Does not isolate downstream capacitive load

  • Stage delay now dependent on downstream stages


Class ended here

Class Ended Here


Power implications

Power Implications

  • What’s the power impact of partial swing?


Back to rail

Back to Rail

  • How make it go to rail?


Transmission gate

Transmission Gate


Level restorer

Level Restorer


Level restorer1

Level Restorer


Level restore

Level Restore

  • What issue arises here?


Level restore1

Level Restore

  • What issue arises here?


Tristate

Tristate

  • Sometimes want to be able to not drive a line

    • Bus driven from different places

    • I/O port – sometimes read, sometime write


Tristate driver

Tristate Driver


Tri state drivers

Tri-State Drivers


Next week

Next week

  • No new assignment now

    • (will get new one after midterm)

  • Class Monday

  • Midterm Wednesday

    • No lecture

    • Midterm 7-9pm in this room

  • Class Friday


Midterm everything through today

Midterm(Everything through today)

  • Restoration

  • Implement or identify gate / logic function

  • Estimate performance for circuit

  • Estimate/reduce energy for circuit

  • Size transistors in gate/netlist

  • Variation impact

  • Scaling

  • Ratio and pass tr circuits fair game

  • Synchronous/clocking not on midterm


Ideas

Ideas

  • There are other logic disciplines

  • We have the tools to analyze

  • Pass Transistor Logic

    • Possibly smaller, faster

    • Not rail-to-rail

      • Techniques to restore

    • Cascading without buffering  slow

    • Tristate Drivers


  • Login