Ese370 circuit level modeling design and optimization for digital systems
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ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Day 19: October 22, 2010 Pass Transistor Logic. Today. Pass Transistor Logic Muxes Performance Composition Logic Tristates. Behavior. O=S*A + S*/B. S. A. B. Delay. Assume R 0 /2 drive 10C 0 load

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ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems

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ESE370:Circuit-Level Modeling, Design, and Optimization for Digital Systems

Day 19: October 22, 2010

Pass Transistor Logic


Today

  • Pass Transistor Logic

    • Muxes

    • Performance

    • Composition

    • Logic

    • Tristates


Behavior

  • O=S*A + S*/B

S

A

B


Delay

  • Assume R0/2 drive

  • 10C0 load

  • What else need to know?

    • Cdiff=CSB or CDB

    • Assume Cdiff≈Cgate

5

2

5


Day 10

Capacitances

  • GS, GB, GD, SB, DB, SD


Day 10

Contact Capacitance

  • n+ contacts are formed by doping = diffusion

  • Depletion under contact

    • Contact-Body capacitance

  • Depletion around perimeter of contact

    • Also contact-Body capacitance


Day 10

Contact/Diffusion Capacitance

  • Cj – diffusion depletion

  • Cjsw – sidewall capacitance

  • LS – length of diffusion

LS


Delay

5

2

5


Delay


CMOS Equivalent


CMOS Delay

  • O=S*A + S*/B


What’s different?

  • What’s different about the output?


Output ok?

  • Is the output usable?


CMOS DC Transfer Function


After CMOS Inverter


What does this do?


Cascade Functional?


Voltage Drop

  • Voltage drop across any number of series transistors is one Vth

  • Think about two series transistors as one transistor of twice the length


Day 9

Pinch Off

  • When voltage drops below VT, drops out of inversion

    • Occurs when: VGS-VDS< VT

  • Conclusion:

    • current cannot increase with VDS once VDS> VGS-VT

    • current must adjust so that VDS= VGS-VT

    • If current dropped to zero, then would invert and conduct again…


Performance?

  • Assume R0/2 drive

  • 10C0 load

  • Cdiff=Cgate

5

2

5


What does this do?

A

B


Performance

  • R0/2 drive

  • 10C0 load

5

2

5


Performance

  • R0/2 drive

  • 10C0 load


Not Isolating

  • Does not isolate downstream capacitive load

  • Stage delay now dependent on downstream stages


Class Ended Here


Power Implications

  • What’s the power impact of partial swing?


Back to Rail

  • How make it go to rail?


Transmission Gate


Level Restorer


Level Restorer


Level Restore

  • What issue arises here?


Level Restore

  • What issue arises here?


Tristate

  • Sometimes want to be able to not drive a line

    • Bus driven from different places

    • I/O port – sometimes read, sometime write


Tristate Driver


Tri-State Drivers


Next week

  • No new assignment now

    • (will get new one after midterm)

  • Class Monday

  • Midterm Wednesday

    • No lecture

    • Midterm 7-9pm in this room

  • Class Friday


Midterm(Everything through today)

  • Restoration

  • Implement or identify gate / logic function

  • Estimate performance for circuit

  • Estimate/reduce energy for circuit

  • Size transistors in gate/netlist

  • Variation impact

  • Scaling

  • Ratio and pass tr circuits fair game

  • Synchronous/clocking not on midterm


Ideas

  • There are other logic disciplines

  • We have the tools to analyze

  • Pass Transistor Logic

    • Possibly smaller, faster

    • Not rail-to-rail

      • Techniques to restore

    • Cascading without buffering  slow

    • Tristate Drivers


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