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CASPER Open Source Hardware Current and Future ADC’s

CASPER Open Source Hardware Current and Future ADC’s. Dan Werthimer and CASPER Collaborators. http:// casper.berkeley.edu. Using Moores Law for Telescope Arrays.

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CASPER Open Source Hardware Current and Future ADC’s

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  1. CASPER Open Source Hardware Current and Future ADC’s Dan Werthimer and CASPER Collaborators http://casper.berkeley.edu

  2. Using Moores Law for Telescope Arrays Infrastructure – Construction Costs Telescopes & Drives, Feeds, Receivers, Analog Electronics, Fibers, Software, Gateware(costs don’t decrease rapidly) Operating Costs – Operating Budget Digital Computing Hardware (beamformers, correlators, spectrometers, VLBI, pulsar, RFI mitigation, computing, storage) Throw away hardware every 5-6 years (cheaper, easier to maintain, 16X) year 6: roach 7, 100Gbit switch year 12: Roach 13, Tbit switch

  3. Allen Telescope Array • 6.1-meter offset Gregorian (2.4-meter secondary) • Designed with Moores Law in Mind

  4. ATA-42 Operational October 2007

  5. BeowulfCluster Like General Purpose Architechture Dynamic Allocation of Resources, need not be FPGA based

  6. Existing Multi-purpose Hardware • BEE2 (5 2VP70-7, 20 GB, 18 CX4) • iBOB (1 2VP50-7, 8 MB, 2 CX4) • MiniRoach (simple Virtex5 test board, spectrometer) • Roach (Virtex5, 4x10Gbit CX4, QDR SRAM, DRAM, Linux CPU) • Bee3 (4*Virtex5, CX4, DRAM, Microsoft, BeeCube) • SERENDIP 5 (2V6000, 2V1000, 4 ADC’s 128 Msps) • 10 Gbe Switches (HP, Foundry, Fujitsu….) • 10 Gbe cables (Gore…. – optical, copper)

  7. 10 Gbit Ethernet Switches, NIC’s • HP – Procurve 6 to 8 ports CX4, 24-48 1Gbe • Fujitsu – 12 port, 20 port, 28 port • Arista - 28 port, SFP+ ($300/port) • Sun – 4300 port - 20Gbit Infiniband ($300/port) (big enough for SKA already) • Myricom – 10 Gbe NIC boards (PCIe) ($600)

  8. CX4 cables (future: SFP+) • Gore CX4 10Gbe cables (1, 2, 3, 15 meter…) about $65 each (not infiniband cables) (see cable length memo for V2Pro 1-3 Meter max) Active CX4 Cables – 45 meter max Optical CX4 Cables

  9. Where to get tested boards • Build and test them yourself (cheapest for large Q)) • iBOB, iADC, Roach, enclosures, power supply, DRAM iBOB mounting plates, iBOB cables, iBOB front panels Digicom Electronics Mo Ohady, mo@digicom.org Upcoming Roach Enclosures: KAT – 1.3U, RFI shielded, $100, nice! NRAO – 3U, optional synthesizer, attenuator/gain (from digicom electronics)

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  11. Current ADC Boards ADC2x1000-8 (dual 1GSa/sec, single 2Gsps, 8 bit) ADC1x3000-8 (3GSa/sec, 8 bit) ADC 64ADCx64-12 (64x 64MSa/sec, 12 bit) ADC4x250-8 (quad 250MSa/sec, 8 bit) katADC (dual 1.5GSa/sec, 8 bit, with gain, atten, synth) ADC2x550-12 (dual 550 Msps, 12 bit) ADC2x400-14 (dual 400 Msps, 14 bit) ADC1x5000-8 (1x5Gsps,2x2.5Gsps,4x1.25G sps – Taiwan) ADC1x1000-12 (optically isolated 12 bit 1Gsps – JPL)

  12. Misc. Boards • Programmable Attenuator/Gain (ATA, NRAO) 4 GHz BW, -16 to +16 dB in 0.5 db step, Notch Filter (or minicircuits, $50, programableatten/gain) • 1 PPS distribution amplifier box • VSI connector (converts ZDOC to VSI (VLBI)) • Dual DAC Board: Dual 16-bit, 1000 Msps • DAC board, 9 bits, 1.5 Gsps • Dual Dac Board, 9 bits, 1.5 Gsps

  13. Future ADC’s? 1/3 of the cost of a wide band correlator is breaking the IF band up into sub-bands with analog mixers, filters and frequency synthesizers before the digitizers. introduces calibration problems – stitching the bands back together is tricky  Desire WIDE BAND DIGITIZERS

  14. 20 Gsps ADC-FGPA-10Gbe board20 Gsps 8 bit Agilent ADC 20 Gsps 5 bit E2V ADC 80 Gsps 8 bit Fujitsu Hittite, National, AdsantecVirtex 6 FPGA 6 SFP+ ports 120 Gbpsxaui 100 Gbpsinfiniband 60 Gbps 10 Gbe

  15. e2V 20 Gsps 5 bit ADC

  16. e2V 20Gsps ADC no drift interleaved (SiGe)

  17. e2V 20 Gsps ADC • ADC with 5-bit Resolution Using Interleaved e2v Core Technology • 10 GHz Differential CML AC Coupled Symmetrical Input Clock Required • 600 mVpp Analog Input (Differential AC Coupled) • ADC Synchronization Signal (CML), CML Output Format • Digital Interface (SPI) with Reset Signal: • – Output Mode Selection (Data Only, PRBS Only, Scrambled Data) • – Gain Control (±10%), Offset Control (±30 mV) • – Per Channel Sampling Delay Adjust (0-10 ps Range) • – Global Delay Adjust (0-25 ps Range), Test Modes (VOL, VOH) • Power Supplies: Single 3.3V (2.5V Outputs) • Power Dissipation: 10W • EBGA240 Package (RoHS, 1.27 mm Pitch) • • Full Power Input Bandwidth (–3 dB) up to 8 GHz • • Band Flatness: < 1 dB from DC to 4 GHz • • Fsampling = 20 GSps, Fin = 4 GHz • – ENOB = 4.5 bit • – SFDR = 35 dBc

  18. Preliminary Characterization results • 4 channels acquisitions (preliminary, no calibration) • 5 bits per channel • Each ADC core @ 5GSps • Analog Input : -1dBFS @ 6.4GHz

  19. Casper Advisory Board Matthew Bailes, John Ford, Yashwant Gupta, Justin Jonas, Glenn Jones, Alan Langman, Jason Manley, Aaron Parsons, Jonathan Weintroub, Dan Werthimer Last Years’s Report On Casper web site Constructive Criticism Ideas for Future Directions, Long Term Strategy How best to collaborate Organizational Structure Anything else  REPORT

  20. MOVIE!!! (9X speed up) • Building Spectrometer • Correlator

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