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IEEE P1149.7, a complementary superset of the IEEE 1149.1 standard

Squeezing the power out of a Debug and Test Interface (DTI). IEEE P1149.7, a complementary superset of the IEEE 1149.1 standard. Agenda. What is IEEE P1149.7? What are the benefits? How is it added to my system? How does it work? Summary. What is IEEE P1149.7?.

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IEEE P1149.7, a complementary superset of the IEEE 1149.1 standard

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  1. Squeezing the power out of a Debug and Test Interface (DTI) IEEE P1149.7, a complementary superset of the IEEE 1149.1 standard

  2. Agenda • What is IEEE P1149.7? • What are the benefits? • How is it added to my system? • How does it work? • Summary TI Public Data

  3. What is IEEE P1149.7? • What is IEEE 1149.1 (JTAG)? • Connection for manufacturing test (BSDL) • Connection for debugging software TI Public Data

  4. Standards Focus1149.1 vs. P1149.7 1149.1 P1149.7 Boundary Scan: Finding card level connectivity issues Compliance: Preserving boundary scan for System on a Chip (SoC) Test Capability: Features for debug Apps TI Public Data

  5. What is IEEE P1149.7? • What is IEEE 1149.1 (JTAG)? • Connection for manufacturing test (BSDL) • Connection for debugging software • What is IEEE P1149.7? • A new IEEE standard currently in process • P1149.7 is not a replacement for 1149.1 • P1149.7 uses 1149.1 as its foundation • P1149.7 provides 1149.1 extensions • P1149.7 provides 2-pin operating modes TI Public Data

  6. MIPI Origins Objective – define a backwards compatible minimum pin debug interface Strategy – requirements gathering, technical debate Tactics – solicit competing proposals, choose a winner Result – P1149.7 was handily selected as winning proposal vs. SWD Collaboration with Nexus consortium Objective – Compare common needs, explore common solution Strategy - Joint meetings, compare requirements Tactics - Specifications reviewed, incorporate feedback Result – Agreement to pursue IEEE standard because of large field of use IEEE PAR approved Test, Debug, and backwards IEEE 1149.1 compatibility considerations Specification reviewed and revision underway now Presumed Result – IEEE 1149.7 standard in early 2008 P1149.7 History and Status TI Public Data

  7. What are the benefits? Feature Benefit Do more with less Do more with less Preserve Investment Preserve Investment Innovation / Customization Innovation / Customization TI Public Data

  8. Extending JTAG JTAG Pins Required=6 Core A Core B SW Driver TDI TMS TCLK TDO EMU0 EMU1 TDI TMS TCLK TDO EMU0 EMU1 Emulator TCLK TCLK TMS TMS TDI TDI TDO TDO EMU0 EMU0 EMU1 EMU1 TI Public Data

  9. Extending JTAG JTAG Pins Required=6 Core A Core B Communication (4) 0xcoffee SW Driver TDI TMS TCLK TDO EMU0 EMU1 TDI TMS TCLK TDO EMU0 EMU1 Instrumentation (2) Emulator TCLK TCLK TMS TMS TDI Read Mem TDI TDO TDO EMU0 EMU0 EMU1 EMU1 • IEEE1149.1 example: Data path is from TDI through cores and out TDO. TI Public Data

  10. Extending JTAG JTAG Pins Required=4 JTAG Pins Required=6 Core A Core B SW Driver TDI TMS TCLK TDO EMU0 EMU1 TDI TMS TCLK TDO EMU0 EMU1 Emulator TCLK TCLK TCLK TCLK Switch to 1149.7 TMS TMS TMS TMSC TMS TMS TDI TDI TDI TDI TDO TDO TDO TDO EMU0 EMU0 EMU0 EMU0 EMU1 EMU1 EMU1 EMU1 Mode=JTAG Mode=advanced • Use adapters to prototype with existing IEEE1149.1 HW and SW. • IEEE1149.7 starts in 1149.1 mode for compatibility. • Switch the Adapter to IEEE1149.7 mode by sending a command. • TMS is now TMSC. • TDI and TDO are now optional. Optional signal TI Public Data

  11. Extending 1149.1 Pins Required=2 Pins Required=4 Core A Core B SW Driver TDI TMS TCLK TDO EMU0 EMU1 TDI TMS TCLK TDO EMU0 EMU1 Emulator TCLK TCLK TCLK TMS TMS 0xcoffee TMS TMSC TMS TDI TDI TDI TDO TDO TDO 0xcoffee EMU0 EMU0 EMU0 EMU1 EMU1 EMU1 Mode=Advanced • EMU0 and EMU1 are typically used for to gather large amounts communication with a target application • Using Background Data eXchange (BDX) and Custom Data eXchange (CDX), target information can be transferred. • For maximum compatibility, CDX can be used to carry manufacturer defined protocols. TI Public Data

  12. Extending 1149.1 Pins Required=2 Core A Core B SW Driver TDI TMS TCLK TDO EMU0 EMU1 TDI TMS TCLK TDO EMU0 EMU1 Emulator TCLK TCLK TMSC TMS TMS TMSC TDI TDI TDO TDO EMU0 EMU0 EMU1 EMU1 Mode=Advanced TI Public Data

  13. IEEE P1149.7 Connection Topologies When all chips have Class 4 or Class 5 TAPs the 4-pin topologies may be operated as a 2-pin topology TI Public Data

  14. Key Control Concepts • Extend functionality of BYPASS and IDCODE instructions • (“overload” these instructions) • Keep new command structure invisible to existing 1149.1 TAPs • Create commands without using TDI or TDO • Use commands to create registers without changing IR/DR scan paths TI Public Data

  15. Overloading the Bypass Instruction(using Zero-bit DR-Scans (ZBS)) Method: • IR register set to BYPASS or IDCODE instruction by: • IR-Scan or • Test-Logic-Reset • ZBS = CaptureExitUpdate • The number of consecutive ZBSs are counted to create a control level that specifies the overloaded function • This is performed by standard IEEE 1149.1 TAP controller state sequences BYPASS IR Register TI Public Data

  16. Zero-Bit Scans Create Control Levels Key: • Count the number of Zero-Bit-Scans (ZBS) to change the definition of BYPASS instruction. • Lock control level when the Shift-DR state is reached. 1…. 2…. 3…. Lock Control Level at 3. BYPASS IR Register TI Public Data

  17. Creating a Control Level • Example: Steps to create a control level 3 • IR-Scan with BYPASS instr. • ZBS • ZBS • ZBS • Example: Steps to create a control level 5 • IR-Scan with BYPASS instr. • ZBS • ZBS • ZBS • ZBS • ZBS BYPASS instruction Increment control level from 0 to 1 Increment control level from 1 to 2 Increment control level from 2 to 3 BYPASS instruction Increment control level from 0 to 1 Increment control level from 1 to 2 Increment control level from 2 to 3 Increment control level from 3 to 4 Increment control level from 4 to 5 TI Public Data

  18. IEEE1149.7 - Debug and Test Tech. Binder BDX Bulk Data Transfer Instrumentation Sources CDX Custom Data Transfer BDM (Freescale)/ SWD (ARM)/other Power down test logic when not used Power Test Test and Private Interface Modes “All industry debug and test IP co-exists behind a standard Interface” Standard interface benefits tools suppliers and users 1149.7 Debug/Test Framework JTAG Boundary Scan Applications TAPs Narrow (2) or Wide (4) • SW directed mode switches between JTAG modes and advanced modes. Software drivers always use IEEE state sequences. • Framework for multiple debug and other technologies • IEEE 1149.1 signaling used at start-up • SW directed mode switches between JTAG modes and advanced modes TI Public Data

  19. Deployment Profiles JTAG Optimized serialization of TMS, TDI, Ready, and TDO Multiple formats BDX Pause and Idle states provide instrumentation channel Pin and BW Utilization CDX Shift_DR state may be used to overlay any custom protocol Extensibility (non-JTAG functions) Chip power and reset controller managing interface power Power Every microwatt counts Test Specialty functions Test and private interface modes Minimal Most Moderate Flash, CPLDs, FPGAs Sophisticated SOC SOC or Micro-Controller Deployment Profile TI Public Data

  20. 1149.7 “Classes” • IEEE 1149.1 Extensions • Class T0 – Assure IEEE Compliance for chips with multiple TAPs • Class T1 – Add control functions (e.g. functional reset, power) • Class T2 – Add performance features for series • Class T3 – Add Star configuration • Advanced Two-Pin Operation • Class T4 – Add two pin operation • Class T5 – Add instruction/custom pin use to two pin operation TI Public Data

  21. IEEE 1149.7 Summary • Do More with Less: Lower pin count • Remaining backwards compatible with Si IP and Tools • Gain additional debug capability TI Public Data

  22. Backup

  23. IEEE 1149.7 Classes • Ensure compliance with 1149.1 to enhance compatibility with industry test infrastructure • After Test-Logic-Reset (TLR) multi-TAP devices: • Conform to mandatory 1149.1 instruction behavior • 1-bit DR-Scan for bypass instruction • Addresses stacked die and multi-chip module needs Class T0 Class T1 • Power: Test logic power-down, etc. • Performance: • Shorten multi-chip scan chains with 1-bit IR bypass • Glue-less star configuration • Pins: Less pins and more functions • Faster downloads to target • Equivalent performance with fewer pins • Instrumentation (BDX) • Customization (CDX) • 4 Power Down modes friendly to: Board Test, Chip Test, and Application Debug • Chip Level Bypass • Built-in Chip Select Mechanism • 2 pins provide scan, Test-Logic-Reset (TLR), and instrumentation (serialized transactions) • Download specific modes (Target Input only) • 2x Clock rate and optimized transactions • Concurrent Debug and Instrumentation using same pins • Instrumentation of data passed during Run-Test-Idle, Pause-DR, and Pause-IR states • Custom technologies can use the test access port pins in Shift-DR state. (ex: SWD, BDM, etc. ) Class T2 Class T3 Class T4 Class T5 TI Public Data

  24. P1149.7 – Adds capability to 1149.1 = the same TCK/TAP state rate as IEEE 1149.1 = 1.17X the TCK/TAP state rate as IEEE 1149.1 = 1.3X the TCK/TAP state rate as IEEE 1149.1 = 2X the TCK/TAP state rate as IEEE 1149.1 1 bits/TAP state 2 bits/TAP state 1.5 bits/TAP state 1.7 bits/TAP state “Minimizing Changes/Maintaining Performance” • The same or better performance than IEEE1149.1 may be achieved in some cases • With advanced protocol • Falling–edge to falling edge timing allows doubling TCK rate • The amount of information transferred is minimized to boost performance • Two or less bits are transferred/TAP controller state in some cases • If a device supports SSCAN modes, performance can improve more. 2*TCK rate 20 MHz 40 MHz 20 MHz Emulator 1149.7 logic Existing controller Chip 1149.7 logic Existing Si IP Narrow (2-pins) or Wide (4-pins) • IEEE 1149.7 added • May be added to existing controller • IEEE 1149.7 added • No changes to existing Si IP TI Public Data

  25. Series Bypass • Uses TAP selection and bypass bit to: • improve series conneted devices scan performance using 1-bit chip bypass for very long scan chains • Create a “firewall” to protect system operation when DTC is connected or disconnected from the TS I want to access this one! Total Chain=100 TAP1 TAP2 TAP1 TAP2 TAP1 38-bit IR 24-bit IR 16-bit IR 16-bit IR 6-bit IR Total Chain=8 TAP1 and TAP2 frozen in IDLE state. TAP1 and TAP2 frozen in IDLE state. TAP1 1-bit bypass 1-bit bypass 6-bit IR Chip Level Bypass Chip Level Bypass TI Public Data

  26. Situation at Power-Up • At power up, you can have the bypass as the default (JScan1 scan format) • Protects TAPs from spurious signal • Prevents core corruption during “hot” connections • Command sequence makes TAPs visible. Command sequence is transparent to IEEE1149.1 devices allowing a mix of IEEE1149.1 and IEEE1149.7 devices. 1149.7 Device 1149.7 Device 1149.1 Device TAP1 and TAP2 frozen in TLR state. TAP1 and TAP2 frozen in TLR state. TAP1 Configuration at Power UP 1-bit bypass 1-bit bypass 6-bit IR 1149.7 Device 1149.7 Device 1149.1 Device TAP1 TAP2 TAP1 TAP2 TAP1 Configuration after “firewall” lowered. 38-bit IR 24-bit IR 16-bit IR 16-bit IR 6-bit IR TI Public Data

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