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Lec 2 Aug 31 review of lec 1 continue Ch 1 course overview performance measures

Lec 2 Aug 31 review of lec 1 continue Ch 1 course overview performance measures Ch 1 exercises quiz 1. Levels of Program Code. High-level language Level of abstraction closer to problem domain Provides for productivity and portability

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Lec 2 Aug 31 review of lec 1 continue Ch 1 course overview performance measures

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  1. Lec 2 Aug 31 • review of lec 1 • continue Ch 1 • course overview • performance measures • Ch 1 exercises • quiz 1

  2. Levels of Program Code • High-level language • Level of abstraction closer to problem domain • Provides for productivity and portability • Assembly language • Textual representation of instructions • Hardware representation • Binary digits (bits) • Encoded instructions and data

  3. Components of a Computer §1.3 Under the Covers • Same components forall kinds of computer • Desktop, server,embedded • Input/output includes • User-interface devices • Display, keyboard, mouse • Storage devices • Hard disk, CD/DVD, flash • Network adapters • For communicating with other computers The BIG Picture

  4. Inside the Processor (CPU) • Datapath: performs operations on data • Control: sequences datapath, memory, ... • Cache memory • Small fast SRAM memory for immediate access to data • Several levels of cache

  5. Inside the Processor • AMD Barcelona: 4 processor cores

  6. AMD Barcelona – some features

  7. Abstractions • Abstraction helps us deal with complexity • Hide lower-level detail • Instruction set architecture (ISA) • The hardware/software interface • Application binary interface • The ISA plus system software interface • Implementation • The details underlying and interface The BIG Picture

  8. A Safe Place for Data • Volatile main memory • Loses instructions and data when power off • Dynamic RAM (50 to 70 nanosecs) • Static RAM (used for cache) • Non-volatile secondary memory • Magnetic disk (5 to 20 millisecs) (30 to 100 times less expensive than DRAM) • Flash memory • Optical disk (CDROM, DVD)

  9. Technology Trends • Electronics technology continues to evolve • Increased capacity and performance • Reduced cost DRAM capacity

  10. Defining Performance §1.4 Performance • Which airplane has the best performance?

  11. Response Time and Throughput • Response time • How long it takes to do a task • Throughput • Total work done per unit time • e.g., tasks/transactions/… per hour • How are response time and throughput affected by • Replacing the processor with a faster version? • Adding more processors?

  12. Relative Performance • Define Performance = 1/Execution Time • “X is n time faster than Y” • Example: time taken to run a program • 10s on A, 15s on B • Execution TimeB / Execution TimeA= 15s / 10s = 1.5 • So A is 1.5 times faster than B

  13. Measuring Execution Time • Elapsed time • Total response time, including all aspects • Processing, I/O, OS overhead, idle time • Determines system performance • CPU time • Time spent processing a given job • Discounts I/O time, other jobs’ shares • Comprises user CPU time and system CPU time • Different programs are affected differently by CPU and system performance

  14. CPU Clocking • Operation of digital hardware governed by a constant-rate clock Clock period Clock (cycles) Data transferand computation Update state • Clock period: duration of a clock cycle • e.g., 250ps = 0.25ns = 250×10–12s • Clock frequency (rate): cycles per second • e.g., 4.0GHz = 4000MHz = 4.0×109Hz

  15. CPU Time • Performance improved by • Reducing number of clock cycles • Increasing clock rate • Hardware designer must often trade off clock rate against cycle count

  16. CPU Time Example • Computer A: 2GHz clock, 10s CPU time • Designing Computer B • Aim for 6s CPU time • Can do faster clock, but causes 1.2 × clock cycles • How fast must Computer B clock be?

  17. Instruction Count and CPI • Instruction Count for a program • Determined by program, ISA and compiler • Average cycles per instruction • Determined by CPU hardware • If different instructions have different CPI • (weighted) average CPI affected by instruction mix

  18. CPI Example • Computer A: Cycle Time = 250ps, CPI = 2.0 • Computer B: Cycle Time = 500ps, CPI = 1.2 • Same ISA • Which is faster, and by how much? A is faster… …by this much

  19. CPI in More Detail • If different instruction classes take different numbers of cycles • Weighted average CPI Relative frequency

  20. CPI Example • Alternative compiled code sequences using instructions in classes A, B, C • Sequence 1: IC = 5 • Clock Cycles= 2×1 + 1×2 + 2×3= 10 • Avg. CPI = 10/5 = 2.0 • Sequence 2: IC = 6 • Clock Cycles= 4×1 + 1×2 + 1×3= 9 • Avg. CPI = 9/6 = 1.5

  21. Check yourself • A given application written in Java runs in 15 seconds on a desktop processor. A new Java compiler is released that requires only 0.6 as many instructions as the old compiler. Unfortunately, it increases the CPI by 1.1. How long do we expect the application to take to complete when compiled with the new compiler? • 15 x 0.6 / 1.1 = 8.2 sec • 15 x 0.6 x 1.1 = 9.9 sec • 15 x 1.1 / 0.6 = 27.5 sec

  22. Performance Summary • Performance depends on • Algorithm: affects IC, possibly CPI • Programming language: affects IC, CPI • Compiler: affects IC, CPI • Instruction set architecture: affects IC, CPI, Tc The BIG Picture

  23. Exercise 1.2.1 For a color display using 8 bits for each primary color (R, G, B) per pixel and with a resolution of 1280 x 800 pixels, what should be the size (in bytes) of the frame buffer to store a frame? Each frame requires 1280 x 800 x 3 = 3072000 ~ 3 Mbytes If a computer has 3 GB memory to store such frames, how many frames can be stored? 3 x 109 / 3 x 106 ~ 1000 frames

  24. Exercise 1.3 Consider 3 processors P1, P2 and P3 with same instruction set with clock rates and CPI given below: clock rate CPI P1 2 GHz 1.5 P2 1.5 GHz 1.0 P3 3 GHz 2.5

  25. Exercise 1.3 Consider 3 processors P1, P2 and P3 with same instruction set with clock rates and CPI given below: clock rate CPI P1 2 GHz 1.5 P2 1.5 GHz 1.0 P3 3 GHz 2.5 1.3.1. Which processor has the highest performance? Suppose the program has N instructions. Time taken to execute on P1 is = 1.5 N / (2 x 109) = 0.75 N x 10-9 Time taken to execute on P2 is = N/ (1.5 x 109) = 0.66 N x 10-9 etc.

  26. Exercise 1.3 Consider 3 processors P1, P2 and P3 with same instruction set with clock rates and CPI given below: clock rate CPI P1 2 GHz 1.5 P2 1.5 GHz 1.0 P3 3 GHz 2.5 1.3.2. If the processors each execute a program in 10 seconds, find the number of cycles and the number of instructions.

  27. Exercise 1.3 Consider 3 processors P1, P2 and P3 with same instruction set with clock rates and CPI given below: clock rate CPI P1 2 GHz 1.5 P2 1.5 GHz 1.0 P3 3 GHz 2.5 1.3.2. If the processors each execute a program in 10 seconds, find the number of cycles and the number of instructions. Time taken to execute on P1 is = 1.5 N / (2 x 109) = 0.75 N x 10-9 = 10 So N = 1.33 x 1010

  28. Power Trends §1.5 The Power Wall • In CMOS IC technology ×30 5V → 1V ×1000

  29. Reducing Power • Suppose a new CPU has • 85% of capacitive load of old CPU • 15% voltage and 15% frequency reduction • The power wall • We can’t reduce voltage further • We can’t remove more heat • How else can we improve performance?

  30. Uniprocessor Performance §1.6 The Sea Change: The Switch to Multiprocessors Constrained by power, instruction-level parallelism, memory latency

  31. Multiprocessors • Multicore microprocessors • More than one processor per chip • Requires explicitly parallel programming • Compare with instruction level parallelism • Hardware executes multiple instructions at once • Hidden from the programmer • Hard to do • Programming for performance • Load balancing • Optimizing communication and synchronization

  32. Manufacturing ICs • Yield: proportion of working dies per wafer §1.7 Real Stuff: The AMD Opteron X4

  33. AMD Opteron X2 Wafer • X2: 300mm wafer, 117 chips, 90nm technology • X4: 45nm technology

  34. Integrated Circuit Cost • Nonlinear relation to area and defect rate • Wafer cost and area are fixed • Defect rate determined by manufacturing process • Die area determined by architecture and circuit design

  35. SPEC CPU Benchmark • Programs used to measure performance • Supposedly typical of actual workload • Standard Performance Evaluation Corp (SPEC) • Develops benchmarks for CPU, I/O, Web, … • SPEC CPU2006 • Elapsed time to execute a selection of programs • Negligible I/O, so focuses on CPU performance • Normalize relative to reference machine • Summarize as geometric mean of performance ratios • CINT2006 (integer) and CFP2006 (floating-point)

  36. CINT2006 for Opteron X4 2356 High cache miss rates

  37. SPEC Power Benchmark • Power consumption of server at different workload levels • Performance: ssj_ops/sec • Power: Watts (Joules/sec)

  38. SPECpower_ssj2008 for X4

  39. Pitfall: Amdahl’s Law • Improving an aspect of a computer and expecting a proportional improvement in overall performance §1.8 Fallacies and Pitfalls • Example: multiply accounts for 80s/100s • How much improvement in multiply performance to get 5× overall? • Can’t be done! • Corollary: make the common case fast

  40. Fallacy: Low Power at Idle • Look back at X4 power benchmark • At 100% load: 295W • At 50% load: 246W (83%) • At 10% load: 180W (61%) • Google data center • Mostly operates at 10% – 50% load • At 100% load less than 1% of the time • Consider designing processors to make power proportional to load

  41. Pitfall: MIPS as a Performance Metric • MIPS: Millions of Instructions Per Second • Doesn’t account for • Differences in ISAs between computers • Differences in complexity between instructions • CPI varies between programs on a given CPU

  42. Concluding Remarks • Cost/performance is improving • Due to underlying technology development • Hierarchical layers of abstraction • In both hardware and software • Instruction set architecture • The hardware/software interface • Execution time: the best performance measure • Power is a limiting factor • Use parallelism to improve performance §1.9 Concluding Remarks

  43. Anatomy of a Computer Output device Network cable Input device Input device

  44. Anatomy of a Mouse • Optical mouse • LED illuminates desktop • Small low-res camera • Basic image processor • Looks for x, y movement • Buttons & wheel • Supersedes roller-ball mechanical mouse

  45. Through the Looking Glass • LCD screen: picture elements (pixels) • Mirrors content of frame buffer memory

  46. Opening the Box

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