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Lullaby Music Box

Lullaby Music Box. Abstract:

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Lullaby Music Box

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  1. Lullaby Music Box Abstract: Generation of simple songs using Digilent Inc.’s D2-DIO2 Combo development board. The project accepts user input for song selection and drives a piezo-electric speaker to generate the sound required for the notes. Corresponding LEDs light up as each note is played. FIT - ECE-5572 by Elias Victor

  2. Approximate Resources Required • FPGA allowing a minimum of: • 550 Slices • 300 Slice Flip Flops • 800 4-input Look Up Tables (LUTs) • 20 Bonded Input/Output Blocks (IOBs) • 1 Global Clock Buffer (GCLK) • User I/O interfaces including: • 8 Slide switches • 16 LEDs FIT - ECE-5572 by Elias Victor

  3. Project Milestones • Search for project idea • Implement preliminary Verilog-based design • Convert from Verilog to VHDL (X-HDL3) • Add I/O devices (slide switches & LEDs) • Add more songs • Test and troubleshoot FIT - ECE-5572 by Elias Victor

  4. Idea Quest • Focus on colleges, universities, and vendor websites and libraries: • http://www.xup.msu.edu/students/examples.htm • http://www.altera.com/support/examples/exm-index.html • http://www.engr.sjsu.edu/crabill/ • http://www.stanford.edu/class/ee108a/ • http://www.digilentinc.com/ • Search library catalogs for Digital System Design textbooks and lab workbooks. FIT - ECE-5572 by Elias Victor

  5. Project Origins • Idea originated from a Verilog-based laboratory exercise at the San Jose State University Electrical Engineering Department by instructor Eric Crabill (http://www.engr.sjsu.edu/crabill/). • Digilent’s DIO2 board demo example (Dio2Demo.vhd) allowed for the incorporation of multiple songs “light show” by adding the use of eight slide switches and LEDs. FIT - ECE-5572 by Elias Victor

  6. Original Verilog Designby Eric Crabill (San Jose State University) • Rudimentary playback (counter in player) • Limited I/O capabilities (d2btn) FIT - ECE-5572 by Elias Victor

  7. Original Design Description • The “CLK_DIV” module slows the D2 board’s 50MHz clock to 195KHz using an 8-bit counter and stops the clock divider from toggling as long as the D2 push button (“RST”) remains pressed. • The “PLAYER” module determines which note designation to play next, at what tempo the song should play, and inserts the required pauses between notes by toggling the “HUSH” signal accordingly. FIT - ECE-5572 by Elias Victor

  8. Original Design Description • The “PIANO” module reads in the “NOTE” designation to play next, decodes the designation into the proper counter value that signifies the frequency to use to toggle the “SPEAKER” port, and stops toggling as long as the “HUSH” signal is asserted (‘1’). • Since there is no analog signal anywhere in the system, a piezo-electric speaker (NOT a buzzer – a buzzer is limited to a single frequency) capable of generating sounds from a toggling digital input signal is used. For this project, I used a “Projects Unlimited” speaker (part# APS-100) which I purchased from “Mouser Electronics” (www.mouser.com). The Mouser part number is 665-APS-100 and it’s cost is between $1.50 and $2.00. The speaker has a frequency range between 500Hz and 20KHz. Radio Shack no longer sells Piezo-electric speakers, only buzzers, which would not work for this project. FIT - ECE-5572 by Elias Victor

  9. My Expanded Design • Added eight 128x5-bit ROM modules (one for each song) and loaded them with the proper sequence of “notes” and “hushes”. • Simplified Digilent’s (Dio2Demo.vhd) module to only deal with the 8 slide switches (one switch per song) and the 15 LEDs. Added to it a process to light up the LED associated with each note (sixteen notes, sixteen LEDs). FIT - ECE-5572 by Elias Victor

  10. My Expanded Design • Modified the player module by connecting to it the eight ROMs with the songs and the d2led (lights up when song playback is paused). • Added a state machine to the player module to read in the state of the slide switches and determine which song to play next. Each song is handled by its own state. FIT - ECE-5572 by Elias Victor

  11. DIO2 Switches and Songs • Legend: • TTLS – “Twinkle, Twinkle Little Star” • MHALL – “Mary Had A Little Lamb” • OMDHF – “Old McDonald Had A Farm” • PP – “Pin Pon” (Spanish) • BDP – “Barquito De Papel” (Spanish) • DBTB – “Down By The Bay” • YAMS – “You Are My Sunshine” • ILYFE – “I Love You For Ever” FIT - ECE-5572 by Elias Victor

  12. DIO2 LEDs and Notes • Legend: • “L” stands for “low” (lower pitch) • “H” stands for “high” (higher pitch) • “b” and “f” in “LBb”, “Eb”, “Gb”, “Ab”, “HBb” and “Df” stand for flat FIT - ECE-5572 by Elias Victor

  13. Process to Turn On Lights (dio2.vhd)

  14. TTLS = “Twinkle, Twinkle Little Star” MHALL = “Mary Had A Little Lamb” OMDHF = “Old McDonald Had A Farm” PP = “Pin Pon” BDP = “Barquito De Papel” DBTB = “Down By The Bay” YAMS = “You Are My Sunshine” ILYFE = “I Love You For Ever” Player Module State Machine Diagram

  15. Player State Machine Source (player.vhd) (Continues on next slide) -- State machine controlling which song is being played. PROCESS (clk_div, swtReg) BEGIN IF (clk_div'EVENT AND clk_div = '1') THEN CASE nextState IS WHEN whichSong => -- Figure out which state to go to next -- depending on the slide switches positions. IF (swtReg = "00000000") THEN nextState <= pausePlay; ELSIF (swtReg = "00000001") THEN nextState <= playTTLS; ELSIF (swtReg = "00000010") THEN nextState <= playMHALL; ELSIF (swtReg = "00000100") THEN nextState <= playOMDHF; ELSIF (swtReg = "00001000") THEN nextState <= playPP; ELSIF (swtReg = "00010000") THEN nextState <= playBDP; ELSIF (swtReg = "00100000") THEN nextState <= playDBTB; ELSIF (swtReg = "01000000") THEN nextState <= playYAMS; ELSIF (swtReg = "10000000") THEN nextState <= playILYFE; ELSE nextState <= pausePlay; END IF; WHEN pausePlay => next_hush <= '1'; -- hush, we are paused. theled <= '1'; -- acknowledge that play has been paused (d2led goes ON) nextState <= whichSong; -- A STATE FOR EACH OF THE OTHER SONGS FOLLOW --

  16. Player State Machine Source (player.vhd) – Representative Song WHEN playTTLS => -- Play “Twinkle, Twinkle Little Star” theled <= '0'; -- d2led off means we are playing. -- Increment counter on every clock cycle. -- Clock frequency is now 195 Khz. ttls_tempo <= ttls_tempo + 1; -- Check to see if tempo counter has reached -- the end. As long as the counter is counting -- the note will keep playing. Once the end -- is reached, the counter is reset. IF (ttls_tempo = "11111111111111") THEN -- Reset tempo counter so it can start the -- count for the next note or hush. ttls_tempo <= "00000000000000"; -- Get the next note or hush by incrementing -- to the next address in the ROM. ttls_note_addr <= ttls_note_addr + "0000001"; -- If the high order bit of the data is a "1", -- then HUSH needs to be asserted. This should -- keep the player from playing while the tempo -- counter counts to the end. -- Otherwise, get the next note and disable hush. IF (ttls_data(4) = '1') THEN next_hush <= '1'; ELSE next_note <= ttls_data(3 DOWNTO 0); next_hush <= '0'; END IF; END IF; -- End of song has been reached, set ROM address -- to start up at the beginning of the song again. IF (ttls_note_addr = "1100110") THEN ttls_note_addr <= "0000000"; END IF; nextState <= whichSong; -- Go back to whichSong state

  17. Player State Machine Source (player.vhd) -- A “Twinkle, Twinkle Little Star” - LIKE STATE GOES HERE FOR EACH OTHER SONG -- WHEN OTHERS => -- Happens when more than one switch is turned on. -- Quiet down and turn on d2led. next_hush <= '1'; -- hush, we are paused. theled <= '1'; ; -- acknowledge that play has been paused (d2led goes ON) -- Go to whichSong state to figure out what to play next. nextState <= whichSong; END CASE; END IF; END PROCESS; -- End of state machine.

  18. “Twinkle, Twinkle Little Star” ROM Source (ttls_rom.vhd) (Continues on next slide) -- After entity definition -- ARCHITECTURE translated OF ttls_rom IS SIGNAL ttls_data_tmp : std_logic_vector(4 DOWNTO 0); -- Define constants to represent each available note. Note -- that the most significant zero was added to each note to -- let the system know that it is not a "hush". CONSTANT LA : std_logic_vector(4 downto 0) := "00000"; CONSTANT Bb : std_logic_vector(4 downto 0) := "00001"; -- same as LA# CONSTANT LB : std_logic_vector(4 downto 0) := "00010"; CONSTANT LC : std_logic_vector(4 downto 0) := "00011"; CONSTANT Db : std_logic_vector(4 downto 0) := "00100"; -- same as C# CONSTANT D : std_logic_vector(4 downto 0) := "00101"; CONSTANT Eb : std_logic_vector(4 downto 0) := "00110"; -- same as D# CONSTANT E : std_logic_vector(4 downto 0) := "00111"; CONSTANT F : std_logic_vector(4 downto 0) := "01000"; CONSTANT Gb : std_logic_vector(4 downto 0) := "01001"; -- same as F# CONSTANT G : std_logic_vector(4 downto 0) := "01010"; CONSTANT Ab : std_logic_vector(4 downto 0) := "01011"; -- same as G# CONSTANT HA : std_logic_vector(4 downto 0) := "01100"; CONSTANT HBb : std_logic_vector(4 downto 0) := "01101"; -- same as HA# CONSTANT HB : std_logic_vector(4 downto 0) := "01110"; CONSTANT HC : std_logic_vector(4 downto 0) := "01111"; -- Define constant to represent "hush". CONSTANT HUSH : std_logic_vector(4 downto 0) := "11111";

  19. “Twinkle, Twinkle Little Star” ROM Source (ttls_rom.vhd) (Continues on next slide) BEGIN ttls_data <= ttls_data_tmp; PROCESS (ttls_addr) VARIABLE my_ttls_data : std_logic_vector(4 DOWNTO 0); BEGIN CASE ttls_addr IS WHEN "0000000" => my_ttls_data := LC; WHEN "0000001" => my_ttls_data := HUSH; WHEN "0000010" => my_ttls_data := LC; WHEN "0000011" => my_ttls_data := HUSH; WHEN "0000100" => my_ttls_data := G; WHEN "0000101" => my_ttls_data := HUSH; WHEN "0000110" => my_ttls_data := G; WHEN "0000111" => my_ttls_data := HUSH; WHEN "0001000" => my_ttls_data := HA; WHEN "0001001" => my_ttls_data := HUSH; WHEN "0001010" => my_ttls_data := HA; WHEN "0001011" => my_ttls_data := HUSH; WHEN "0001100" => my_ttls_data := G; WHEN "0001101" => my_ttls_data := G; WHEN "0001110" => my_ttls_data := G; WHEN "0001111" => my_ttls_data := HUSH; WHEN "0010000" => my_ttls_data := F; WHEN "0010001" => my_ttls_data := HUSH; WHEN "0010010" => my_ttls_data := F; WHEN "0010011" => my_ttls_data := HUSH; WHEN "0010100" => my_ttls_data := E; WHEN "0010101" => my_ttls_data := HUSH; WHEN "0010110" => my_ttls_data := E; WHEN "0010111" => my_ttls_data := HUSH; WHEN "0011000" => my_ttls_data := D; WHEN "0011001" => my_ttls_data := HUSH; WHEN "0011010" => my_ttls_data := D; WHEN "0011011" => my_ttls_data := HUSH; WHEN "0011100" => my_ttls_data := LC; WHEN "0011101" => my_ttls_data := LC; WHEN "0011110" => my_ttls_data := LC; WHEN "0011111" => my_ttls_data := HUSH; WHEN "0100000" => my_ttls_data := G; WHEN "0100001" => my_ttls_data := HUSH; WHEN "0100010" => my_ttls_data := G; WHEN "0100011" => my_ttls_data := HUSH; WHEN "0100100" => my_ttls_data := F; WHEN "0100101" => my_ttls_data := HUSH; WHEN "0100110" => my_ttls_data := F; WHEN "0100111" => my_ttls_data := HUSH; WHEN "0101000" => my_ttls_data := E; WHEN "0101001" => my_ttls_data := HUSH; WHEN "0101010" => my_ttls_data := E; WHEN "0101011" => my_ttls_data := HUSH; WHEN "0101100" => my_ttls_data := D; WHEN "0101101" => my_ttls_data := D; WHEN "0101110" => my_ttls_data := D; WHEN "0101111" => my_ttls_data := HUSH; WHEN "0110000" => my_ttls_data := G; WHEN "0110001" => my_ttls_data := HUSH; WHEN "0110010" => my_ttls_data := G; WHEN "0110011" => my_ttls_data := HUSH; WHEN "0110100" => my_ttls_data := F;

  20. “Twinkle, Twinkle Little Star” ROM Source (ttls_rom.vhd) WHEN "0110101" => my_ttls_data := HUSH; WHEN "0110110" => my_ttls_data := F; WHEN "0110111" => my_ttls_data := HUSH; WHEN "0111000" => my_ttls_data := E; WHEN "0111001" => my_ttls_data := HUSH; WHEN "0111010" => my_ttls_data := E; WHEN "0111011" => my_ttls_data := HUSH; WHEN "0111100" => my_ttls_data := D; WHEN "0111101" => my_ttls_data := D; WHEN "0111110" => my_ttls_data := D; WHEN "0111111" => my_ttls_data := HUSH; WHEN "1000000" => my_ttls_data := LC; WHEN "1000001" => my_ttls_data := HUSH; WHEN "1000010" => my_ttls_data := LC; WHEN "1000011" => my_ttls_data := HUSH; WHEN "1000100" => my_ttls_data := G; WHEN "1000101" => my_ttls_data := HUSH; WHEN "1000110" => my_ttls_data := G; WHEN "1000111" => my_ttls_data := HUSH; WHEN "1001000" => my_ttls_data := HA; WHEN "1001001" => my_ttls_data := HUSH; WHEN "1001010" => my_ttls_data := HA; WHEN "1001011" => my_ttls_data := HUSH; WHEN "1001100" => my_ttls_data := G; WHEN "1001101" => my_ttls_data := G; WHEN "1001110" => my_ttls_data := G; WHEN "1001111" => my_ttls_data := HUSH; WHEN "1010000" => my_ttls_data := F; WHEN "1010001" => my_ttls_data := HUSH; WHEN "1010010" => my_ttls_data := F; WHEN "1010011" => my_ttls_data := HUSH; WHEN "1010100" => my_ttls_data := E; WHEN "1010101" => my_ttls_data := HUSH; WHEN "1010110" => my_ttls_data := E; WHEN "1010111" => my_ttls_data := HUSH; WHEN "1011000" => my_ttls_data := D; WHEN "1011001" => my_ttls_data := HUSH; WHEN "1011010" => my_ttls_data := D; WHEN "1011011" => my_ttls_data := HUSH; WHEN "1011100" => my_ttls_data := LC; WHEN "1011101" => my_ttls_data := LC; WHEN "1011110" => my_ttls_data := LC; WHEN "1011111" => my_ttls_data := LC; WHEN "1100000" => my_ttls_data := LC; WHEN "1100001" => my_ttls_data := HUSH; WHEN "1100010" => my_ttls_data := HUSH; WHEN "1100011" => my_ttls_data := HUSH; WHEN "1100100" => my_ttls_data := HUSH; WHEN "1100101" => my_ttls_data := HUSH; WHEN "1100110" => my_ttls_data := HUSH; WHEN OTHERS => my_ttls_data := HUSH; END CASE; ttls_data_tmp <= my_ttls_data; END PROCESS; END translated;

  21. Left for Future Improvement or Projects • Add digital-to-analog converter to output the corresponding analog signal, amplify it, and play it through a regular speaker with some type of volume control. • Increase the 16-note limit to allow for a larger range of songs to be played. • Exercise the rest of the DIO2 board’s controls by perhaps displaying the song title in the LCD, using the 7-segments to show different light patterns as the music plays, etc. FIT - ECE-5572 by Elias Victor

  22. Project Summary • Expanded preliminary Verilog-based design (by Eric Crabill from SJSU) to play not just a musical scale, but an actual song. • Converted design to VHDL. • Added the use of input/output devices (DIO2 slide switches and LEDs) by incorporating a modified version of Digilent’s DIO2 module into design. • Added seven more songs. The notes for each song were stored in individual ROM VHDL modules. FIT - ECE-5572 by Elias Victor

  23. Acknowledgements • Eric Crabill – Making lab exercises available to more than just his class. • Tamas Kasza – DIO2 incorporation and state machine understanding and LOTS of patience. • Deborah Crosby – Verilog to VHDL conversion and for helping me understand the function of my own reset signal. • Tien-Hsiang Lo – Verilog. • Jonathan Mason – Sharing of VGA source code and willingness to help. • Chris List – Allowing me to use his book. • Dr. Kepuska – Taking on the challenge (AHPL  VHDL). FIT - ECE-5572 by Elias Victor

  24. Questions & Demo FIT - ECE-5572 by Elias Victor

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