Introduction to IC Test

1. Introduction to IC Test Tsung-Chu Huang (黃宗柱) Department of Electronic Eng. Chong Chou Institute of Tech. Email: tch@dragon.ccut.edu.tw 2004/05/10

2. Syllabus & Chapter Precedence Introduction Modeling Logic Simulation Fault Modeling Fault Simulation Testing for Single Stuck Faults Design for Testability Test Compression Built-In Self-Test

3. Built-In Self-Test (BIST) Objectives • To Reduce input/output pin signal traffic. • Permit easy circuit initialization and observation. • Eliminate as much test pattern generation as possible. • Achieve fair fault coverage on general class of failure mode. • Reduce test time. • Execute at-speed testing. • Test circuit during burn-in.

4. Built-In Self-Test (BIST) Issues • Area overhead • Performance degradation • Fault coverage • Ease of Implementation • Capability for system test • Diagnosis capability

5. Typical BIST Techniques Test Good (or Not) • Stored Vector Based (Pattern Generated) • Microinstruction support • Stored in ROM • Algorithmic Hardware Test Pattern Generators • Counter • Linear Feedback Shift Register • Cellular Automata • FSM (ASM) Based Design with BIST

6. Classification • Forms • Off-Line • Functional • Structural • On-Line • Concurrent • Parallel • Pipeline • Asynchronous • Non-concurrent • Level • Production Testing • Field Testing • TPG for BIST • Exhaustive Testing • Pseudo-random Testing • Weighted • Adaptive • Pseudo-exhaustive Testing • Counter-Based: Syndrome, Constant-Weight • LFSR-Based: Shift/Scan, XOR, Condensed, Cyclic

7. General BIST Architecture Centralized Distributed CUT TPG CUT ORA Separate DIST DIST DIST DIST TPG ORA CUT TPG CUT ORA BISTC Embedded TPG ORA TPG ORA TPG ORA BISTC CUT CUT TPG: Test Pattern Generator, ORA: Output Result Analyzer CUT: Circuit under Test, BISTC: BIST Controller

8. Specific BIST Architecture

9. Specific BIST Architecture

10. Specific BIST Architecture (1) CSBL n CUT (C or S) PIs n m MUX m POs PRPG Counter MUX SISR 1 k 1 • Centralized and Separate Board-Level BIST [Benowitz 75] • Use only one Signature Register • Tests repeat m times to reduce hardware cost

11. Specific BIST Architecture (2) LFSR LFSR Combinational circuit Combinational circuit SA SA Combinational Sequential (BEST) (Circular BIST) • Pseudo random testing • Hardware overhead is low • Test length can be long for CUT with random-pattern resistant faults.

12. Specific BIST Architecture (3) RTS R1 R3 CUT (S) MISR PRPG Sin Clocks Controls Sout R2 R4 SISR SRPG BIST controller • Combine LSSD Scan Chain and BIST • Can insert scan points to reduce test length for random-pattern resistant faults

13. Specific BIST Architecture (4) LOCST R2 SRSG SISR R1 CUT (S) PIs POs Si S0 SRL SRL Sin On-chip monitor (OCM) Sin Error signal Error-detection circuitry Control signals • Boundary scan is required to unify the test architecture • Single scan chain may cause high test time overhead.

14. Specific BIST Architecture (5) CBIST N / T CBIST Circuitry Comparator Normal inputs EN PRPG N / T MUX CUT (C) MISR Normal outputs • Detect test patterns from normal inputs sequence • Once a pattern is detected, compress the response and tick the test clock. • If waited too long, insert a test pattern from PRPG.

15. Specific BIST Architecture (6) LFSR Shift register LFSR Circuit Under Test S R S R S R CUT CUT SA SA (CEBS) (STUMPS) Centralized and Embedded BIST with BS Self-Testing using MISR & Parallel SRSG low cost version of RTS or LOCST

16. Specific BIST Architecture (7) LFSR 1/8 3/4 1/2 7/8 1/2 LFSR Based Weighted Pseudo Random Test

17. Specific BIST Architecture (8) SST CUT Combinational PI PO • Similar to MISR but without LFSR part

18. Specific BIST Architecture (9) HP Focus Chip (Stored Pattern) • Chip Summaries • 450,000 NMOS devices, 300,000 Nodes • 24MHz Clocks, 300K bits of on-chip ROM • Used in HP9000-500 computer • BIST Micro-program • Use microinstructions dedicated for testing • 100K-bit BIST micro program in CPU ROM • Executes 20 million clock cycles • Greater than 95% stuck-at coverage • A power-up test used in system test, filed test, and wafer test

19. Specific BIST Architecture (10A) Motivation of BILBO Combinational Circuit Di Dn Ci Si Normal MISR RPG Scan

20. Specific BIST Architecture (10B) Built-in Logic Block Observation (Koenemann ‘79) Z1 Z2 Zn ... B1 BILBO1 ... B2 C1 Si 0 MUX D Q D Q D Q D Q BILBO2 1 ... Q Q Q Q S0 C2 Q1 Q2 Qn-1 Qn BILBO3 ... B1 B2 BILBO 0 0 shift register 0 1 reset 1 0 MISR (input * constant * LFSR) 1 1 parallel load (normal operation) C3

21. Syllabus & Chapter Precedence Introduction Modeling Logic Simulation Fault Modeling Fault Simulation Testing for Single Stuck Faults Design for Testability Test Compression Built-In Self-Test IDDQ Testing

22. VLSI Testing Theoretical Classification • By Signals Modes: • Voltage Test • Current Test • By Signal Types: • Digital (Logic) Testing • Analogue Testing

23. IDDQ Testing Basic Concept IDD IDD VDD IDD t t Current Sensor

24. IDDQ Testing Advantages • Can detect more physical defects including bridging defects. • The error response is easily detected by deep submicron era. • The ATPG is easily to design. • The test size (pattern count) is usually small. • Current test technology is sufficient.

25. Types of IDDQ Test Architecture ATE Automatic Test Equipment ATE Automatic Test Equipment BICS Built-In Current Sensor Test Fixture Off-Chip Current Monitor DUT Device under Test DUT Device under Test DUT Device under Test External Motoring Test Fixture Built-In Current Test QTAG (Quality Test Action Group),1993

26. Power Dissipation VDD VDD • Static Power Dissipation • Dynamic Power Dissipation • Switching Transient • (Short-circuit) Current • Loading Dissipation • (Charging/Discharging of CL)

27. Power Dissipation Nano-meter Pd Deep- submicron Sub-micron Micron Psc Ps 1mm 0.5mm 80nm 50%

28. Power Dissipation Static Dissipation • Quiescent State • Input steady for enough time • Either P- or N- Network is off • Theoretically, IDDQ→0 • However, small static dissipation due to • Reverse bias leakage ISB • Gate leakage • Considerable in deep submicron era