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Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs. Tomasz S. Czajkowski and Stephen D. Brown University of Toronto. Start with HDL Convert HDL to gates Gates to logic components on FPGA Place and route Get Results Program FPGA. FPGA CAD Background. Motivation.

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Functionally linear decomposition and synthesis of logic circuits for fpgas

Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs

Tomasz S. Czajkowski


Stephen D. Brown

University of Toronto

Fpga cad background

Start with HDL Circuits for FPGAs

Convert HDL to gates

Gates to logic components on FPGA

Place and route

Get Results

Program FPGA

FPGA CAD Background

Motivation Circuits for FPGAs

  • Synthesis of XOR-based logic circuits is

    • Difficult

    • Time Consuming

  • Very useful for circuits that deal with

    • Arithmetic

    • Error correction

    • Communication

  • Focus on area optimization in this work

Why use xor gates

c Circuits for FPGAs





Why Use XOR Gates?

Basic idea

Express a k-input logic function in a truth table Circuits for FPGAs(2n rows, 2m columns, n+m=k)

Find a set of linearly independent columns,also known as a basis

Express each column asa weighted sum of basis functions

Column Selector Functions are the weighting factors





G1 = c



G2 = d


f = bc + ad

Basic Idea

Finding basis functions

Use Gaussian Elimination to determine the basis columns Circuits for FPGAs

Perform elementary row operations (add rows, swap rows)

Reduce the matrix until for each row the column with the left most 1 has only 0s below it


The leftmost 1 element of each non-zero row points to the basis vector in the original truth table


Linear Independence is guaranteed

Number of basis vectors is minimum

Finding Basis Functions

Express each column in terms of g 1 and g 2

Trivial for columns of all zeros or those that are either G Circuits for FPGAs1 or G2

Other columns Ci are expressed as

h1 and h2 are the solution to the following equation

Express Each Column in terms of G1 and G2

Easy to see

Create column selector functions

For each basis function, G Circuits for FPGAs1 and G2, record for which columns h1i and h2i are 1

Create Truth Tables H1 and H2 to identify columns in which h1i and h2i are 1.

H1 and H2 are the selector functions

Create Column Selector Functions

H1 = b

H2 = a


Put G Circuits for FPGAs1, G2, H1 and H2 together to synthesize function f

G1 = c

H1 = b


G2 = d

H2 = a


How to order variables

Partition variables between rows (bound set) and columns (free set)

Which one is the better choice?

For a function with k variables the largest number of possible variable partitions is






How to order variables?

Heuristic variable ordering procedure

ab (free set)






Heuristic Variable Ordering: Procedure


  • Step 1:

    • Starting with n=2, determine all possible partitions with bound set size of 2.

      • Pick k/2 best such that each variable is in exactly one grouping.

  • Step 2:

    • For (n=4; n < m; n=n*2)

      • Repeat procedure in Step 1, except now group groupings generated in the step for n/2.

  • Step 3:

    • If m is not a power of 2, use the generated groupings to form valid bound sets and pick the best one (longest step).

  • Step 4:

    • Reorder variables in f to match the best grouping of size m found.









Heuristic variable ordering runtime
Heuristic Variable Ordering: Runtime (free set)

  • For k=16, m=8 the number of partitions tested is 154, versus 12870 possible partitions

    • 120 tested for n=2, picked 8 best

    • 28 tested for n=4, picked 4 best

    • 6 tested for n=8, picked 2 best

  • If m was 7 then in addition we would test combinations of valid partitions formed from initial inputs, as well as n=2 and n=4 groups.

    • 4*6*10 = 240

    • Thus for a 16 variable function we are testing at most388 partitions (instead of 11440 partitions)

Basis and selector optimization
Basis and Selector Optimization (free set)

  • Variable ordering can change the area of the final implementation of the logic function

  • A set of basis/selector functions for a given variable partition is a minimum set, but

    • Not unique

    • Other sets can be better (less costly to implement) than the one we found

  • We need to explore alternate solutions


Same function as before (free set)

bound set {b,c}

free set {a,d}

Basis-selector pairs are:


We can replace G2 with G’ and then we have basis-selector pairs:










Multi output synthesis
Multi-Output Synthesis (free set)

  • Put truth tables side by side

  • Apply Gaussian Elimination to all functions simultaneously

    • Create a common set of basis functions

    • Selector functions are different for each output

Example 2 bit adder

C (free set)out



Synthesize S1 and Cout as

Example: 2-bit Adder

Circuit for example 2
Circuit for Example 2 (free set)

Let x0y0 be Cin

Duplication reduction
Duplication Reduction (free set)

  • Replace a duplicate function (related by equality or complementation) with a wire/inverter

  • Store a list of functions with k inputs or less created in the process of synthesis

    • If the same function is repeated then connect to itvia a wire/inverter

  • Both methods are utilized frequently

Results (free set)

  • 99 MCNC circuits tested

    • 25 XOR based, as determined by prior research

      • Circuit known to have a lot of XOR gates inside

      • Set used in many XOR–based logic synthesis papers

    • 74 non-XOR

  • Compiled BDS-PGA 2.0, ABC, and our tool (FLDS) under Windows XP

    • Dual Xeon 2.8GHz with 2GB of RAM

  • Synthesized each circuit with BDS-PGA 2.0,ABC and FLDS.

  • Used ABC to map logic into 4-LUTs

Xor circuits 1 of 2
XOR circuits (1 of 2) (free set)

  • Cordic

    • two 23-input functions, small area, fast synthesis

    • Neither ABC nor BDS-PGA can synthesize it well

Xor circuits 2 of 2
XOR circuits (2 of 2) (free set)

  • Good results

    • Win on both area and depth

  • Synthesis is fast

Circuits not included in comparison
Circuits not included in comparison (free set)

  • Failed to synthesize with BDS-PGA 2.0

  • Two circuits failed to synthesize with BDS-PGA 2.0

    • Ex1010

      • ABC results: 4094 LUTs, Depth 8, Time 1.52 seconds

      • FLDS results: 1063 LUTs, Depth 7, Time 13.94 seconds, Cone size set to 12

      • Comparison

        • Area: -74.04 %

        • Depth: -12.5 %

    • Misex3

      • ABC results: 1093 LUTs, Depth 6, Time 0.44 seconds

      • FLDS results: 493 LUTs, Depth 10, Time 3.8 seconds, Cone size set to 16

      • Comparison

        • Area: -54.89 %

        • Depth: +40.0 %

Interesting experiment
Interesting Experiment (free set)

  • Does FLDS work in tandem with other synthesis tools?

    • Optimize circuit with FLDS and then apply ABC’s optimizations

    • Compared to ABC alone

  • Results:

    • XOR circuits:

      • Area: -24.2 %

      • Depth: -16.2%

    • Non-XOR circuits:

      • Area: -4.25 %

      • Depth: +1%

    • Overall

      • Area: -9.3%

      • Depth: -3.3%

Flds with abc vs abc all circuits included
FLDS with ABC vs. ABC (free set)(all circuits included)

Observations (free set)

  • FLDS is good for XOR based logic

  • Performs reasonably well for non-XOR logic

    • Most gains due to synthesis of multi-outputlogic functions

  • FLDS is fast

    • Runtime in second for functions larger than16 inputs

Future work
Future Work (free set)

  • Look at non-disjoint decomposition

  • Combine with tools such as ABC to synthesize all types of logic well

Acknowledgements (free set)

  • Valavan Manohararajah,Deshanand Singh of Altera Corporation

  • Professors Zvonko G. Vranesic and Jianwen Zhu from the University of Toronto for their input during the course of this research

  • We would also like to take this opportunityto thank Altera Corporation for fundingthis research

Questions? (free set)