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Trigger and DAQ System

Zhao Jing Wei Sept. 2002, BESIII review, Beijing Outline Trigger system Event rate estimation Principle of design Scheme Monte Carlo simulation DAQ system Read Out Online Slow Control Details. Trigger and DAQ System. Trigger System __ Estimation of event rate. Purpose

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Trigger and DAQ System

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  1. Zhao Jing Wei Sept. 2002, BESIII review, Beijing Outline Trigger system Event rate estimation Principle of design Scheme Monte Carlo simulation DAQ system Read Out Online Slow Control Details Trigger and DAQ System

  2. Trigger System __ Estimation of event rate • Purpose • To select all interested events for physics from backgrounds • To suppress background as possible • Event rate after Level 1 can be sustainable for DAQ system

  3. Total trigger rate = good event rate (~2000, LBEPCII = 1  1033 cm-2 s-1) + bhabha rate (~800,to be pre-scaled) + cosmic event rate (<200,from 1500) + beam background rate (<2000Hz,from 13MHz) = ~ 4000 Hz Trigger System__ Estimation of event rate

  4. Trigger System__ Estimation of event rate Backgrounds rate vs beam current At BESII/BEPC

  5. Trigger System__Principle • Challenges to BESIII trigger design • High good event • High Backgrounds • Multi-bunches=93, small bunch spacing=8ns • No dead time design in trigger system • Pipeline processing must be used (Latch-process-decision mode not possible in 8ns) • Latency of trigger signal necessary

  6. Time Reference Detector 0 s FEE pipeline Level 1 3.2s Readout buffer PowerPC switch Ev.Filter Farms Disk Trigger System__Principle • Hardware trigger + software trigger(filter) • FEE signal is splitted to trigger + FEE pipeline • L1 signal 3.2slatency • FEE pipeline clock 40MHz • FEE Control Logic checks L1 with FEE pipeline clock • L1 YES moves pipeline buffer data • L1 No overwritten by new data

  7. Block Diagram of BES III Trigger Global Trigger Logic TOF DISC Hit/Seg Count Track Match MDC DISC Track Seg. Finder Track Finder Energy Balance EMC TrigSum TC Sum Etotal Sum L1P Cluster Counting MU DISC Mu track CLOCK RF TTC 3.2 s

  8. Trigger System__Scheme • One way of the detector signal from FEE is sent to trigger system. • TOF trigger • hit, time and topology information • MDC trigger • checks for a track segment • looks for a track with track segments • counts the number of tracks. • EmC trigger • makes a sum of 24 Crystal signals to form a trigger cell • uses trigger cells to make energy balance

  9. Trigger System__Scheme • Track match • The messages from TOF, EmC, MDC will be used in track Matching to check whether there are matched tracks. • Global trigger • All messages will be sent to global trigger, based on trigger conditions if the event is good is determined. • Level 1 signal • Global trigger will send L1 signal to readout modules of electronics if it is good event.

  10. BLT 9008 2008 TSF cards On FEE TRK CNT GTSF Axial& stereo PTD/TF MDC trigger schemes GLT • Scheme A(AX only): • TSF + TF + TRKCNT • Scheme B(AX+ST): • TSF + GTSF +BLT+PTD+TRKCNT

  11. MDC trigger simulation • Feasibility of trigger scheme study • Trigger efficiency study • Wire in-efficiency influence study • Backgrounds rejecting ability study • Production of configuration data • Track Segment Finding • Track Finding/PTD

  12. Trigger efficiency vs Pt and wire efficiency Configuration: Pt > 120 MeV TSF:Ncomb=8 TSF:Ncomb=24 tracks with Pt>130MeV + Weff>95% TrigEff>95%

  13. BESIII EMC trigger scheme FEE 8ch sum Gain Adj.

  14. EMC Simulation • <20% difference acceptable • Gain adjustment for each crystal+PD+PreAmp chain • Trigger Cell should be at least 4X4 =16 crystals. • 4X6=24 is taken

  15. Summary of Trigger System • Hardware trigger + software filter • L1 latency : 3.2 s • Pipeline clock: 40 MHz • Monte Carlo simulation going well • backgrounds, MDC, EMC trigger schemes • Design scheme drafted • Some modules designed/designing • Further/detailed designing undergoing

  16. BESIII DAQ system__Tasks • Event readout from FEE • Event building • (fragments → sub-events → a full event) • Online event filtering • (L3 trigger, 50% backgrounds suppressed) • Event recording to persistent media • Run control of DAQ system • Monitoring (event, histogram display ...) • Message reporting functions

  17. Data Rate Estimation

  18. Data Volume Estimation • Electronic Channels to be Readout: 40K(30K TDC plus ADC) • Level-1 Trigger Rate: 4KHz(2KHz Good Events) • Event Size: 12KBytes • Data rate after Level 1 will be 49MByte/sec • Data rate to be recorded on tape 37MByte/sec • 1000 times than BESII DAQ System(0.04MByte/sec) • Data volume will be 240TByte/5year

  19. Technologies & Challenges • Multi-level Buffering(module,crate,PC) • Switch Network(Gigabit) • Parallel Computing • Readout from VME • Easy to Upgrade and Port • Data/Message storage and good management Database is needed. • System integration: Easy to operating • Software Engineering: guarantee good quality

  20. Readout Scheme

  21. Readout R&D and Result • Test for VME bus and Network • 3MByte/sec for programming I/O • 13MByte/sec for DMA • 100M Network is OK, it is possible that VME bus readout will be a “bottle-neck” if HPTDC is used. • Require • Readout plus transmitting from VME to PC • Good performance of FEE board, DMA must be adopted • Other techniques R&D, such as S-link plus ROM • VME64x bus

  22. Online System__Event Builder

  23. Online system__Data flow

  24. Online system__Functions Online Farm Node • Event Building • Event Data Formatting • Online Event Filtering • Histogram Filling • Event Classification Farm Supervisor • Keep track of events currently buffered in readout PC • Keep track of events currently processed in Farm Node • Distribute physics events to Online Farm Nodes • Maintain the event record number

  25. Slow Control • Along with BESIII sub-systems designing • A Complex System • Monitoring(temperature, humidity, voltage, gas etc) • Controlling(high voltage, gases etc) • Save/Display history/status information • Purpose • Guarantee safety of device and personnel • Useful information

  26. Slow Control • Strategy • Mature techniques • One wire bus • USB bus for common devices • Database and Web accessing • Commercial Devices • Scheme • Not determined, but Consideration going

  27. Summary of DAQ system • Determined principal part of DAQ scheme • Slow Control scheme will be soon • R&D of DAQ going • Readout model, Online model • Key techniques of Slow Control • Improving software process

  28. Details • The trigger report of Z.A, Liu • The DAQ report ofK.J, Zhu • The Slow Control ofC.S, Gao Thanks!

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