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Fast position resolution silicon detectors

Fast position resolution silicon detectors. Gregor Kramberger , DESY. OUTLINE General properties of position sensitive detectors Column Parallel CCD (CPCDD) Monolithic Active Pixel Detectors (CMOS imager) Depleted Field Effect Transistor Detectors (DEPFET)

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Fast position resolution silicon detectors

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  1. Fast position resolution silicon detectors Gregor Kramberger , DESY • OUTLINE • General properties of position sensitive detectors • Column Parallel CCD (CPCDD) • Monolithic Active Pixel Detectors (CMOS imager) • Depleted Field Effect Transistor Detectors (DEPFET) • Hybrid Active Pixel Detectors (HAPS)

  2. p+ n-Si n+ p+ n-Si up to 1 mm U n+ U Particle tracking Imaging 3.6 eV/pair Only some photons interact each particle leaves a track collection time ~ns order p+ n-Si up to 1 mm up to 1 mm n+ U U Signal Signal Position can be determined – center of gravity To obtain good position resolution – high S/N ratio

  3. N • Segmentation options: • low particle (photons) rate – strip detectors Read-out channels/detector module: N+M When read-out in: series: N+M time units parallel: bigger of [N,M] M Only projections can be obtained. Bottom side perpendicular segmentation or two detectors (each 1D) can be used! • high particle (photons) rate – pixel detectors N Read-out channels/detector module: NxM When read-out in: series: NxM time units parallel: bigger of [N,M] Usually many detector modules are put together to cover the image area! M (silicon is produced in silicon wafer – nowadays already 8” inch)

  4. 15 cm diameter >1m Slicing the rod in typically 300 mm slices (wafers) Detectors diced out of silicon wafers Similar processing as for microelectronics lithographic steps, etching, implantations, PolySi filling

  5. What do we want from one module? A large high resolution “picture” as fast and easy as possible! picture taking rate (frame rate) up to few 10 kHz few 10 cm2 few mm With a lot of effort can be achieved! without severe restriction on operating conditions, electronics (voltage supply etc) needed One of the following requirements can be even more demanding on expense of the others! This talk will try to illustrate different detector options for particle tracking at LC and to some extent their ability to be exploited for X-ray detection! Many common points: with modification same detector concepts can be used for both The further discussion will refer only to pixel detectors!

  6. One can not explain everything -> only the concepts will be presented ! things specific to tracking at LC (material budget – thinning of the detectors, power consumption, mechanics, cooling … will be left out) Division of fast position sensitive detectors with respect to operational principle! • Charge Coupled Devices (CP CCD) • (RAL, Oxford, Liverpool) • Active Pixel Sensor (APS) • - Depleted Field Effect Transistor Detector • (MPI München, Mainz, Bonn) • - Monolithic Active Pixel Sensors (MAPS, CMOS imager) • (IRES Strasbourg, DESY, NIKHEF) • - Hybrid Active Pixel Sensors (HAPS) • (Warshaw, Krakow, Insubria) • (widely used technology for pixel detectors in HEP) Different collaborations working on LC vertex detector (plots taken from their presentations)

  7. V p (epi) p+ (bulk) dep. p1 p2 p3 Fully depleted n- bulk p+ implants p+ CPCCD - Principles of operation p1 p2 p3 CCD is an array of capacitors metal gates oxide • buried channel CDD • potential minimum moved from the surface by n+ • collected charge is a combination of drift and diffusion (drift much faster – high resistive epi-Si) • p/p+ edge works as a reflection layer • MOS gate is superimposed on top of the n+ layer • the depleted region is controlled by the voltage applied to the electrodes (p1,p2,p3) U • PNP CDD • Instead of MOS a p-n-p structure is formed • Larger volume can be depleted and by that higher photon detection efficiency at larger energies • ( used for XMM – Newton )

  8. CPCCD - Readout Asymmetrical n+ doping Only one direction of charge transfer possible both direction of charge transfer possible V p1 p2 p3 p1 p2 sine clocks

  9. Typical frequency 5 MHz Classical CCD: slow – not appropriate for high frame read-out rates factor 2 in speed reset One can use higher frequency in horizontal shift register – some gain in speed, but not enough! Source follower (1st stage of amplification) 2nd stage amplification follows “Classic CCD” Readout time=NxM/nout different frequencies can be used in horizontal shift register Different solution is needed!

  10. TESLA VXD – requires 50 ms read-out/frame in layer 1 – huge challenge ! read-out of column with ~2500 pixels (10x1.3 cm2) in 50 ms (20 kHz frame rate) 1st layer ladder read-out CCD VXD read-out 1.3 cm 650 20 mm pixels 2500 20 mm pixels 2500 20 mm pixels S=13 cm2 10 cm Fast readout speed only with Column parallel readoutnew design – first in the world ! • Serial register omitted • 50 Mpixels/sec from each column • Image section clocked at high frequency • Each column has its own ADC/amplifier (compare to classic CCD) “Column Parallel CCD” Readout time=N/nout

  11. Fast CPCCD – considerations • imagine feeding large capacitance (2-3 nF/cm2) at 50MHz: • Low resistivity gates are required - Polysilicon gates replaced by metallized gates (30% variation in clock amplitudes over CCD - simulations) • Low voltage clocks up to max. 3 V amplitude - to reduce the power heating • high resistive epi-Si to have large area depleted and therefore fast collection • well capacity ~ 20000 e • n+ implant design to enhance charge transfer between cells • +some other things …… Two phase, 50 MHz design pixel size 20 μm  20 μm; Metallized gates + field enhance implant PolySi gates + field enhance implant World’s 1st CPCCD prototype fully designed and operational at 50 MHz Metallized gates PolySi gates SF DC wire bonds

  12. Source follower ( needs reset ) or Direct Coupling ? Wire/bump bond pads Charge Amplifiers DC Voltage Amplifiers SF Read-out chip (CPR-1 chip, 0.25 mm CMOS, 50 MHz) 250 5-bit flash ADCs • Both charge and Voltage amplifier for DC or SF coupling • 5 bit flash ADC • buffer FIFO Wire/bump bond pads FIFO Next iterations will have also: Gain eq. between columns, CDS, clustering ,data sparsification

  13. Problem of CCDs Charge collection efficiency (generated charge clocked through the detector) CTI denotes the loss of charge when shifted from one cell to another TRAPS  - imperfections in Si crystal(capture charge during transfer) radiation induced – radiation damage Charge losses must be very small: CTI~0.0001 with n=2000 Q/Q0=82% • How to reduce CTI: • 2-phase CCD (smaller V) • notch CCD –additional implant • (smaller V Q sees less traps) • fast CCD • (Q has no time to get trapped) – implementation field enhanced implants • pre-injection of dark current to fill the traps • proper operational temperature

  14. CPCCD - Prototype performance Previous prototype – off-shell 3 phase CCD driven at 50 MHz at –70 with pp 3V amplitudes 55Fe spectrum

  15. Pros CP-CCD • Proven technology – a lot of experience • with low resistive epi-Si or PNP-CCD large effective thickness can be reached – good for imaging • large homogeneity of charge collection • small pixel sizes of order (20x20 mm2) – good spatial resolution < 5 mm • Cons CP-CCD • High costs and limited vendor choice ( only MTech is working on them ) • Radiation hardness is questionable (charge transfer over entire detector – CTI degradation) • detectors may need to be operated at lower temperatures

  16. 15 µm MAPS (CMOS imager)- principles of operation -no HV -operation voltage set by CMOS process fill factor = 100% through the center of N well through the center of P well • double-well CMOS process with epitaxial layer • the charge generated by the impinging particle is reflected by the potential barriers due to doping differences and collected by thermal diffusion by the n-well/p-epi diode • large charge spreading (signal shared over many pixels) • “slow” charge collection (t~100 ns – depends on epi-Si) • integration of the circuitry electronics on the same sensor substrate (1st stage of amplification) • useable for detection off photons with few keV (limit set by epi-layer thickness)

  17. Relaxation of excess charge after particle passage Particle track 0 nsec 0 nsec 1 nsec 1 nsec 10 nsec 10 nsec 20 nsec 20 nsec If r of the substrate is high significant contribution of diffused charge from substrate to the total charge

  18. MAPS - Readout Collection (int. time=frame rate) Reset (common row) Output Reset… M2 gate potential

  19. Current prototype’s clock speed 40 MHz At present prototypes only reset and clock signals are needed Last amplification stage common to all Full analog information (all pixel) is read-out in series - slow • Simple readout scheme for the first • prototypes (5 up to now) • a reset cycle (all pixels) – common row reset • cell output is amplified - physical signal: two frames are read-out and subtracted – CDS

  20. Signal/Noise ratio for given event CDS : get rid of FPN, reset noise, 1/f noise

  21. “Large” pixel size and deep submicron technology -> integration of high chip functionality • MIMOSA 6 (being manufactured) • pixel pitch 28x28m2 • 1 array 30x128 pixels – 29 transistors/pixel – instead of 3 • New features: • columns read-out in parallel - max. clock freq.: 30 MHz (CP) • Also 2nd stage amplification and CDSdone on-pixel! • ADC conversion done at the edge of columns • data sparsification integrated at the edge off the chip – zero suppression Chip layout AC coupling capacitor CP read out Single pixel layout Charge storage capacitors 6 clock cycles for row

  22. pixels Analog and digital electronics 1st layer ladder read-out optimistic Column read-out ~5-8 clock cycles will be needed for processing the signal for each pixels in each column 10 cm Analog and digital electronics R/O parallel to the short side of the detector: for TESLA ~ 200 pixel (0.5 cm)/50ms pixels Column read-out ~1 cm less optimistic Analog and digital electronics

  23. MAPS – prototype performance chip size 1.73x1.73 cm2 Wafer view 5 prototypes build so far in different technologies (deep sub m), different pixel sizes, clock frequencies and epilayer thicknesses MIMOSA 5 – large size detector - standard 0.6mm CMOS of AMSwith 14m thick EPI layer(1014cm-3), pixel 17x17m2,well capacity > 10000 e max. CMOS die size 2x2 cm2 ~10% of the total surface Pixel read-out direction • First stitched ladders of few neighboring chips are produced (100 mm between chips – can be reduced to 1 mm – almost no dead area) • simple serial frame read-out – 150 Hz frame rate (full analog information read-out) • problem with fabrication yield!

  24. 55Fe calibration

  25. Large scale prototype test in pion beam To large extent leakage current contribution (shorter frame rate should reduce noise to around 10e) T=0oC

  26. Pros MAPS • low cost (production of 6 6” wafers for example 44000 Euros, 9 USD/cm2 is expected) • standard CMOS process – profiting from huge progress in microelectronic industry: convenient way of design - standard software tools, design kits and libraries, high yield, low power consumption • Radiation hardness – up to few 100 kRad less than 10% degradation in collected charge • low noise due to small gate capacitance (few fF) – theoretically few e - few 10 e • signal processing (1st and 2nd stage amplification) in each individual pixel is possible -> good S/N at high speed • homogeneity of charge collection >97% • pixel sizes of order (25x25 mm2) – could be limited by integration of large number of transistors • Cons MAPS • limited epi-layer thickness and by that usability for detection of photons (deep sub m -maybe no epi) • requirement for 8 metal layers and also analog design rules for CMOS – not very easily found • potential danger of very deep sub-micron technology (trench isolation – charge trapping)

  27. DEPFET - Principles of operation • p-channel JFET or MOSFET integrated on high-ohmic, sidewards-depleted, n-substrate • a local potential minimum is formed by S/D potentials aided by a deep n implantation • (punch-through bias of the pixels) • • electrons are collected in an internal gate close to the surface (collection time few ns) • • the transistor channel current is modulated by charge collected in the internal gate • • the device can be switched on/off by an external (top) gate

  28. Internal gate fills up with: • signal charges • thermally generated charges (leakage current) pulsed clear: pixel dead time < 1% of measuring time

  29. DEPFET - Readout random access to pixels ! • DEPFET Column parallel read-out mechanism: • switch on one row through gate contacts and take pedestal current + signal current • reset the row • switch row on again and take pedestal current • subtract the signal-pedestal • repeat for all rows • do CDS Now: 20 ms – 50 kHz TESLA: 20 ns – 50 MHz a very ambitious but achievable goal • Electronics requirement • Current read-out (@ drain) • Current memory cells

  30. Using different readout scheme the frame read-out time can be reduced to as low as 10 ms (100 kHz frame rate) Drawback is larger power consumption: current prototype development: 128x128 pixels array clocked at 50 MHz expected noise < 100 e (at root temperature) with resolution of < 5mm

  31. DEPFET – prototype performance • DEPFET’s field of use – beside tracking in particle physics: • low energy X ray astronomy XEUS (0.1-30 keV sensitivity) • Medical imaging (autoradiography) - BIOSCOPE (64x64 pixel array of 50x50 mm2) 55Fe (6 keV) - 37 lp/mm ~ 6.7 mm 109Cd (22 keV) - 57 lp/mm ~ 4.3 mm 6 s threshold single pixel device ENC=4-5 e matrix – 69 e (35oC) 1 kHz frame rate - 50 kHz line 75 mm tungsten plate Imaged with sources projections

  32. Real time – space and energy resolution! (different markers can be separated)

  33. Pros DEPFET • low noise due to small gate capacitance (few 10 fF) – theoretically few e • external amplification only in the 2. stage what leads to good signal/noise • the thickness of the substrate can be large - higher efficiency for photons! • Homogeneity of charge collection >95% (achieved with prototypes so far) • pixel sizes of order (25x25 mm2) • Non-linearities < 0.1% within large dynamic range • Radiation hard (deep submicron technology, rad-hard design rules) ????? • Drawback • High cost (8 implantations, 15 masks, 200 technological steps) • less flexible – not suitable for any vendor

  34. chip sensor HAPS - Principles of operation All major HEP experiments concept At LHC MHz frame rate – with noise around 200 e • fast read-out (charge collection times of ns order) • each pixel has its own read-out amplifier • Detection of low-energy photons from the back – large thickness – up to 1 mm - can be depleted • The read-out chip is mounted directly on top of the pixels (bump-bonding) • Problem is in assembly of pixel detector-hybrid: bump bonding – alignment • This limits the pixel detector resolution – minimal bump-bondable size – pixel area limited by the read-out chip! • Large pixel capacitance – higher noise • BUT…, no limit on read-out chip design • possible to detect few keV photons from the back Charge sensitive preamplifiers p+ n- n+

  35. Polyresistor Interleaved pixel Readout pixel readout pitch = n x pixel pitch Small enough for an effective sampling and good spatial resolution Large enough to house the VLSI front-end cell p + n Pixel detector with interleaved pixels Charge carriers generated underneath one ofthe interleaved pixel cells induce a signal on the capacitively coupled read-out pixels, leading to a spatial accuracy improvement by a proper signal interpolation. Silicon On Insulator (SOI) detector Detector:conventional p+-n, DC-coupled: Electronics:conventional bulk MOS technology • Detector handle wafer • High resistive • 300 m thick • Electronics active layer • Low resistive • 1.5 m thick SUCIMA INSULATOR

  36. Interleaved Readout HAPS - Prototype performance The read-out pixels were wire bonded to the readout electronics chip. The BELLE experiment amplifiers and readout chain were used 880 nm laser used to determine CCE <80 mm spot size – scan performed with 2D stage cell size = 100 mm 60 mm Max charge loss ~ 40% In good agreement with estimated values for capacitive network Resolution between 3-10 mm

  37. Pros HAPS • Proven technology – a lot of experience • Very fast - up to few MHz frame rate • good homogeneity of charge collection • no problems with radiation hardness (can sustain 3 orders of magnitude larger doses than others) • large thickness can be depleted – good efficiency for photons • Independent design of the read-out chip • Cons HAPS • High cost (ATLAS and CMS estimation) • Complicated assembly – alignment of hybrids and detectors • higher noise (large pixel capacitance)

  38. SUMMARY There is a bright future for silicon in the field of particle detectors! With new ideas coming and microelectronics industry growing … sky is the limit

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