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ECE 448 Lab 3 FPGA Design Flow Based on Xilinx ISE and Isim. Using Seven-Segment Displays,

ECE 448 Lab 3 FPGA Design Flow Based on Xilinx ISE and Isim. Using Seven-Segment Displays, Buttons, and Switches. Agenda for today. Part 1: Distribution and testing of FPGA boards Part 2: Seven Segment Displays Part 3: User Constraints File Part 4: Buttons and Switches

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ECE 448 Lab 3 FPGA Design Flow Based on Xilinx ISE and Isim. Using Seven-Segment Displays,

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  1. ECE 448 Lab 3 FPGA Design Flow Based on Xilinx ISE and Isim. Using Seven-Segment Displays, Buttons, and Switches.

  2. Agenda for today Part 1: Distribution and testing of FPGA boards Part 2: Seven Segment Displays Part 3: User Constraints File Part 4: Buttons and Switches Part 5: Introduction to FPGA Design Flow based on Xilinx ISE Part 6: Introduction to Lab 3 Part 7: Class Exercise

  3. Part 1 Distribution and Testing of FPGA Boards

  4. Part 2 Seven Segment Displays

  5. Seven Segment Displays

  6. 4-Digit Seven Segment Display

  7. Patterns for Decimal Digits

  8. Patterns for Hexadecimal Digits

  9. Connection to FPGA Pins

  10. Multiplexing Digits

  11. Time-Multiplexed Seven Segment Display

  12. SSD_DRIVER SEG(6..0) Counter UP Counter UP q(k-1..k-2) Counter UP COUNTER UP Counter UP clk AN OC Counter UP rst OC – One’s Complement

  13. Size of the counter 1 ms ≤ 2k * TCLK ≤ 16 ms fCLK = 100 MHz k = ?

  14. Part 3 User Constraint File (UCF)

  15. User Constraint File (UCF) • File contains various constraints for Xilinx • Clock Period • Circuit Locations • Pin Locations • Every pin in the top-level unit needs to have a pin in the UCF

  16. User Constraint File (UCF) - SSD # Seven Segment Displays NET "SEG<0>" LOC = "T17" | IOSTANDARD = "LVCMOS33"; NET "SEG<1>" LOC = "T18" | IOSTANDARD = "LVCMOS33"; NET "SEG<2>" LOC = "U17" | IOSTANDARD = "LVCMOS33"; NET "SEG<3>" LOC = "U18" | IOSTANDARD = "LVCMOS33"; NET "SEG<4>" LOC = "M14" | IOSTANDARD = "LVCMOS33"; NET "SEG<5>" LOC = "N14" | IOSTANDARD = "LVCMOS33"; NET "SEG<6>" LOC = "L14" | IOSTANDARD = "LVCMOS33"; NET "AN<0>" LOC = "N16" | IOSTANDARD = "LVCMOS33"; NET "AN<1>" LOC = "N15" | IOSTANDARD = "LVCMOS33"; NET "AN<2>" LOC = "P18" | IOSTANDARD = "LVCMOS33"; NET "AN<3>" LOC = "P17" | IOSTANDARD = "LVCMOS33";

  17. User Constraint File (UCF) - LEDs # LEDs NET "LED<0>" LOC = "U16" | IOSTANDARD = "LVCMOS33"; NET "LED<1>" LOC = "V16" | IOSTANDARD = "LVCMOS33"; NET "LED<2>" LOC = "U15" | IOSTANDARD = "LVCMOS33"; NET "LED<3>" LOC = "V15" | IOSTANDARD = "LVCMOS33"; NET "LED<4>" LOC = "M11" | IOSTANDARD = "LVCMOS33"; NET "LED<5>" LOC = "N11" | IOSTANDARD = "LVCMOS33"; NET "LED<6>" LOC = "R11" | IOSTANDARD = "LVCMOS33"; NET "LED<7>" LOC = "T11" | IOSTANDARD = "LVCMOS33";

  18. User Constraint File (UCF) CLOCK # Buttons NET "CLOCK" LOC = "V10" | IOSTANDARD = "LVCMOS33";

  19. Part 4 Switches and Buttons

  20. User Constraint File (UCF) Switches # Switches NET "SW<0>" LOC = "T10" | IOSTANDARD = "LVCMOS33"; NET "SW<1>" LOC = "T9" | IOSTANDARD = "LVCMOS33"; NET "SW<2>" LOC = "V9" | IOSTANDARD = "LVCMOS33"; NET "SW<3>" LOC = "M8" | IOSTANDARD = "LVCMOS33"; NET "SW<4>" LOC = "N8" | IOSTANDARD = "LVCMOS33"; NET "SW<5>" LOC = "U8" | IOSTANDARD = "LVCMOS33"; NET "SW<6>" LOC = "V8" | IOSTANDARD = "LVCMOS33"; NET "SW<7>" LOC = "T5" | IOSTANDARD = "LVCMOS33";

  21. Buttons

  22. Connection of Buttons to FPGA Pins

  23. Debouncing Buttons key bounce, tBOUNCE key bounce, tBOUNCE Bouncing period typically smaller than 10 ms

  24. Using DEBOUNCE_RED to Generate Short Pulses (1) RED – Rising Edge Detector

  25. Using DEBOUNCE_RED to Generate Short Pulses (2)

  26. Debouncer Debouncer reset output input clk

  27. Debouncer

  28. k and DD Generics k - width of the counter used to measure the debouncing period DD - debouncing period in clock cycles Values of generics given on the next slide assume that the clock frequency = 100 MHz and thus clock period = 10 ns.

  29. k and DD Generics Option 1 (value used for simulation only): DD = 100 assuming bouncing period < 1 μs = 1000 ns condition: DD*10ns = 1000 ns => DD = 100 k=7 because 2^7 > 100 Option 2 (values used for synthesis, implementation, and experimental testing): DD = 1000000 assuming bouncing period = 10 ms condition: DD*10ns = 10ms => DD = 1,000,000 k=21 because 2^21 > 1,000,000

  30. Rising Edge Detector - RED • Turn a step function into an impulse • Allows a step to run a circuit for only one clock cycle Rising Edge Detector

  31. Rising Edge Detector reset rising edge detector input output clk clk input output

  32. Connection of Buttons to FPGA Pins

  33. User Constraint File (UCF) Buttons # Buttons NET "BTNS" LOC = "B8" | IOSTANDARD = "LVCMOS33"; BTNS NET "BTNU" LOC = "A8" | IOSTANDARD = "LVCMOS33"; BTNU NET "BTNL" LOC = "C4" | IOSTANDARD = "LVCMOS33"; BTNL NET "BTND" LOC = "C9" | IOSTANDARD = "LVCMOS33"; BTND NET "BTNR" LOC = "D9" | IOSTANDARD = "LVCMOS33"; BTNR

  34. Part 5 Hands-on Session on FPGA Design Flow based on Xilinx ISE and Xilinx ISim

  35. Part 6 Introduction to Lab 3 Automated Teller Machine ATM

  36. ATM Services Balance Inquiry (BAL) Cash Withdrawal (COUT) Deposit Cash (CIN) Deposit a Check (CHEC) Change PIN (CPIN)

  37. Step 1: Entering a PIN Number Default Enter PIN using switches Move to STEP 2

  38. Step 2: Choosing an Option Default BTNU (UP) BTNR (RIGHT) BTNL LEFT BTND DOWN BTNS (Enter)

  39. Balance Inquiry • If “Balance Inquiry” chosen first time • For Every other “Balance Inquiry”, display the available balance on 7-segment display • To go to Step 2 BTNS (Enter)

  40. Cash Withdrawal $10 $50 $100 $20 Amount entered using Buttons

  41. Cash Withdrawal • If amount entered is not a multiple of $20 or greater than $500, display • For Insufficient funds, Display • If amount entered is a valid amount, it should blink for 5 seconds on the 7-segment display, and the remaining amount is displayed afterwards.

  42. Cash Deposit $10 $50 $100 $20 Amount entered using Buttons

  43. Cash Deposit • Total deposit amount is displayed on the seven segment • display, starting from 0. • Available Balance = Previous Balance + Deposit Amount • If available balance is greater than the allowed balance ($1500), display • and reset the deposit amount to 0. • If amount entered is a valid amount, it should blink for 5 seconds on the 7-segment display, and the Available Balance is displayed afterwards.

  44. Check Deposit • Check value specified in BCD notation entered using Switches. • Available Balance = Previous Balance + Deposit Amount • If available balance is greater than the allowed balance ($1500), display • and reset the deposit amount to 0. • If amount entered is a valid amount, it should blink for 5 seconds on the 7-segment display, and the Available Balance is displayed afterwards.

  45. Change PIN • New 8-bit PIN entered using Switches • If new PIN matches the old PIN, display • Otherwise update the new PIN

  46. Part 7 Lab Exercise

  47. 16-bit Binary Up-Down Counter

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