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Net Diagnosis using Stuck-at and Transition Fault Models Lixing Zhao* Vishwani D. Agrawal

Net Diagnosis using Stuck-at and Transition Fault Models Lixing Zhao* Vishwani D. Agrawal. Department of Electrical and Computer Engineering Auburn University, AL 36849 USA * Presently with FutureWei Technologies, Inc., Santa Clara, CA 95054 USA. Outline. Motivation Background

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Net Diagnosis using Stuck-at and Transition Fault Models Lixing Zhao* Vishwani D. Agrawal

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  1. Net Diagnosis using Stuck-at and Transition Fault Models Lixing Zhao* Vishwani D. Agrawal Department of Electrical and Computer Engineering Auburn University, AL 36849 USA * Presently with FutureWei Technologies, Inc., Santa Clara, CA 95054 USA VTS 2012: Zhao-Agrawal

  2. Outline • Motivation • Background • Problem Statement • Diagnosis Method • Fault Filtering • Fault Ranking • Net Ranking • Conclusion • References VTS 2012: Zhao-Agrawal

  3. Motivation • Fault diagnosis can bring the yield up in manufacturing rounds by identifying the possible causes of defects in earlier tape-outs. • Net fault diagnosis is an important area of fault diagnosis. Because of the large routing area of modern VLSI devices, the routing interconnection nets are more vulnerable to certain defects. VTS 2012: Zhao-Agrawal

  4. Background • Net defects sometimes have certain complicated characteristics. • Simply using traditional fault models cannot solve the net fault diagnosis problem well. • Using complicated fault models to match the behavior of a net fault is time consuming, not supported by tools, and not suitable for practical use. VTS 2012: Zhao-Agrawal

  5. Problem Statement • Find an effective method for solving the net-fault-diagnosis problem using available software tools. VTS 2012: Zhao-Agrawal

  6. We use test patterns, which have high diagnostic coverage for single stuck-at faults and single transition faults. Y. Zhang and V. D. Agrawal, “A Dianostic Test Generation System,” Proc. International Test Conf., 2010, Paper No. 12.3. Y. Zhang and V. D. Agrawal, “Reduced Complexity Test Generation Algorithms for Transition Fault Diagnosis,” Proc. International Conf. on Computer Design, 2011, pp. 96-101. Diagnostic Test Patterns VTS 2012: Zhao-Agrawal 2012 VTS 6

  7. Diagnostic Procedure • Start with collapsed set of faults. • First Filter (Simple): Test pattern matching. • Second Filter: Primary output (PO) matching. • Discard faults below count thresholds. • Rank order remaining faults. • Map top suspects onto nets. A: patterns detecting fault F B: patterns failing CUT on ATE C Count (F) = |C|/|A| VTS 2012: Zhao-Agrawal

  8. Count for Second Threshold • Set a high threshold for first count; few faults left. • Compute a second PO-specific count D: C ×PO pairs for fault F C ×PO pairs for CUT on ATE E: Hit patterns Count (F) = |E|/|D| VTS 2012: Zhao-Agrawal

  9. Training for Count Thresholds • Set a high threshold for the first filter. • Generate sample circuits by injecting some (e.g., four) randomly chosen faults. • Select second threshold so 90% injected faults survive the two filters. • If necessary, lower the first threshold. VTS 2012: Zhao-Agrawal

  10. Filtering Results VTS 2012: Zhao-Agrawal

  11. Ranking Suspects • Rank filtered fault candidates in a list of key suspects. • Only patterns failing on ATE are simulated. • A structure called erroneous PO-tree (EPO-tree) is constructed for all failing patterns. • Faults are ranked at each PO separately by their total number of appearances in EPO-trees. Failing pattern 1 VTS 2012: Zhao-Agrawal

  12. Diagnostic Experiments • ISCAS’85 circuits. • 200 faulty circuit samples: 1-4 randomly selected faults injected. • Diagnosis: • Diagnosability (Dia): fraction of injected faults found • First hit rank (FHR): Position of an injected fault in the ranked suspect list • Resolution (Res): Ratio of number of diagnosed faults to injected faults VTS 2012: Zhao-Agrawal

  13. Experimental Results Z. Wang, M. Marek-Sadowska and J. Rajski, "Analysis and Methodology for Multiple-Fault Diagnosis,” IEEE Tran on CAD of Integrated Circuits and Systems, March 2006, vol. 25, pp. 558-576. VTS 2012: Zhao-Agrawal

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  15. Net Ranking • Each ranked fault is uncollapsed and all equivalent faults are given the same rank as the parent fault. • Count for a net is the highest rank of any fault on it. • Nets are ranked in order of descending count. VTS 2012: Zhao-Agrawal

  16. Experimental Results VTS 2012: Zhao-Agrawal

  17. VTS 2012: Zhao-Agrawal

  18. Conclusion • Net diagnosis is a practical way of identifying possible sites of defects. • Use of fault models facilitates test generation, fault grading and diagnostic analysis. • Using a variety of fault models may have benefits in diagnosis. • Tests with higher diagnostic coverage may be beneficial. • Basic idea is to gradually narrow down the list of suspects using single fault analysis tools: • Initial filtering only uses collapsed fault list and all test patterns. • Next filtering uses failing PO information, filtered faults and failed patterns. • Suspect ranking uses failed patterns, filtered fault list and PO matching. • Suspected net ranking is based upon the ranked faults and their equivalent fault sets. VTS 2012: Zhao-Agrawal

  19. References • Y. Zhang and V. D. Agrawal, “A Dianostic Test Generation System,” Proc. International Test Conf., 2010, Paper No. 12.3. • Y. Zhang and V. D. Agrawal, “Reduced Complexity Test Generation Algorithms for Transition Fault Diagnosis,” Proc. International Conf. on Computer Design, 2011, pp. 96-101. • N. Sridhar and M. S. Hsiao, “On Efficient Error Diagnosis of Digital Circuits,” Proc. International Test Conference, 2001, pp. 678-687. • S. M. Reddy, H. Tang, I. Pomeranz, S. Kajihara and K. Kinoshita, “On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout,” Proc. International Test Conf. , 2002, pp. 83-87. • Z. Wang, M. Sadowska, and J. Rajski, “Analysis and Methodology for Multiple-fault Diagnosis,” IEEE Tran on CAD of Integrated Circuits and Systems, vol. 25, pp. 558-576, Mar. 2006 • S. Venkataraman and S. B. Drummonds, “Poirot: Applications of a Logic Fault Diagnosis Tool,” IEEE Design and Test of Computers, Jan. 2001, pp. 19-29. • J. Segura and C. F. Hawkins, CMOS Electronics: How It Works, How It Fails,”Wiley- IEEE, Apr. 2004. VTS 2012: Zhao-Agrawal

  20. Thank You . . . VTS 2012: Zhao-Agrawal

  21. Questions VTS 2012: Zhao-Agrawal

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