EE166

1. EE166 PROJECT DESIGN San Jose State University For Dr Parent May 7, 2003

2. Team Members • John Devasia • Ligy Cherian • Rod Davidson • Long Nguyen

3. Design Project Four-Bit Four Function ALU

4. Functions • The four functions performed will be: • Adder • Subtractor • Logical_And • Shift Left

5. Design Specifications • The following specifications shall apply • Implementation of four functions (2-bit control) • Propagation delay of 5 ns or less for the system • Capable of driving a 25 pF load at 200 mHz

6. 4 Bit ALU Schematic

7. Approach • In order to design the ALU, we took the following approach. • Reduced the functions through the use of K-Maps • Implemented the circuit using AOI processes • Split up the system into sub-components for schematic capture, layout, and test • Layout parameters • The cell height will be equal to sixty micrometers. • All vertical routing will be done with metal2, routing between the ALU units will be done with metal3.

8. Min Terms Adder Y = ABC+ABC+ABC+ABC Cout = AB+ACin+BCin Subtractor Y = ABC+ABC+ABC+ABC Cout = CAB+CAB+CAB+CAB Shift LeftLogical And Y= C Y = nand gate Cout = A Y Output Y = YaddAdd+CinSL+YandLA

9. Project Description • The ALU is broken down into sub blocks consisting of: • Inputs • Control/Decoder • Adder/Subtractor • Logical_And • Shift Left / Output Control

10. Block Diagram

11. Timing Considerations Decision Decoder Inverter Inverter Inverter Inverter Inverter Adder O / P X ns 1 .25 1 .25 2 .50 2 .50 1 .25 4 1.0 1 .25 3 .75 1 .25 Total Timing consideration is 4 ns(max timing allotment is 5 ns)

12. Input Schematic Wn = 15um Wp = 19.95 um t = .5 ns(not in critical path) Inputs A, B, Cin Outputs !A, !B, !Cin

13. Input Layout

14. Input Test bench

15. Input Waveform

16. Input LVS-1 @(#)$CDS: LVS version 4.4.6 06/01/2001 20:24 (cds11612) $ Like matching is enabled. Net swapping is enabled. Fixed device checking is enabled. Using terminal names as correspondence points. Compiling Diva LVS rules... Net-list summary for /home/cher5606/LVS/layout/netlist count 33 nets 12 terminals 47 pmos 47 nmos Net-list summary for /home/cher5606/LVS/schematic/netlist count 33 nets 12 terminals 23 pmos 23 nmos

17. Input LVS-2 Terminal correspondence points 1 !A 2 !Add 3 !B 4 !Cadd 5 !Cin 6 !Yadd 7 A 8 Add 9 B 10 Cin 11 gnd! 12 vdd!

18. Input LVS-3 The net-lists match. layout schematic instances un-matched 0 0 rewired 0 0 size errors 0 0 pruned 0 0 active 94 46 total 94 46 nets un-matched 0 0 merged 0 0 pruned 0 0 active 33 33 total 33 33 terminals un-matched 0 0 matched but different type 0 0 total 12 12

19. Decoder Schematic Wn = 12.45um Wp = 14.4 um t = .5 ns Inputs S0, S1 Outputs Add, !Add, Sub, LA, SL

20. Decoder Layout

21. Decoder Testbench

22. Decoder Waveform

23. Decoder LVS-1 @(#)$CDS: LVS version 4.4.6 06/01/2001 20:24 (cds11612) $ Like matching is enabled. Net swapping is enabled. Fixed device checking is enabled. Using terminal names as correspondence points. Compiling Diva LVS rules... Net-list summary for /home/cher5606/LVS/layout/netlist count 33 nets 12 terminals 47 pmos 47 nmos Net-list summary for /home/cher5606/LVS/schematic/netlist count 33 nets 12 terminals 23 pmos 23 nmos

24. Decoder LVS-2 Terminal correspondence points 1 !A 2 !Add 3 !B 4 !Cadd 5 !Cin 6 !Yadd 7 A 8 Add 9 B 10 Cin 11 gnd! 12 vdd!

25. Decoder LVS-3 The net-lists match. layout schematic instances un-matched 0 0 rewired 0 0 size errors 0 0 pruned 0 0 active 94 46 total 94 46 nets un-matched 0 0 merged 0 0 pruned 0 0 active 33 33 total 33 33 terminals un-matched 0 0 matched but different type 0 0 total 12 12

26. Adder Schematic Wn = 19.8 um Wp = 40.5 um tPHL = .4 ns Inputs Add, !Add, A, B, Cin, !A, !B, !Cin Outputs !Yadd, !Cadd

27. Adder Layout

28. Full Adder Testbench

29. Full Adder Waveform

30. Adder LVS-1 @(#)$CDS: LVS version 4.4.6 06/01/2001 20:24 (cds11612) $ Like matching is enabled. Net swapping is enabled. Fixed device checking is enabled. Using terminal names as correspondence points. Compiling Diva LVS rules... Net-list summary for /home/cher5606/LVS/layout/netlist count 33 nets 12 terminals 47 pmos 47 nmos Net-list summary for /home/cher5606/LVS/schematic/netlist count 33 nets 12 terminals 23 pmos 23 nmos

31. Adder LVS-2 Terminal correspondence points 1 !A 2 !Add 3 !B 4 !Cadd 5 !Cin 6 !Yadd 7 A 8 Add 9 B 10 Cin 11 gnd! 12 vdd!

32. Adder LVS-3 The net-lists match. layout schematic instances un-matched 0 0 rewired 0 0 size errors 0 0 pruned 0 0 active 94 46 total 94 46 nets un-matched 0 0 merged 0 0 pruned 0 0 active 33 33 total 33 33 terminals un-matched 0 0 matched but different type 0 0 total 12 12

33. Logical_And Schematic Wn = 3.0 um Wp = 3.0 um t = 350 ps Inputs A, B Outputs !Yand

34. Logical_And Layout

35. Logical_And Testbench

36. Logical_And Waveform

37. Logical_And LVS-1 @(#)$CDS: LVS version 4.4.6 06/01/2001 20:24 (cds11612) $ Like matching is enabled. Net swapping is enabled. Fixed device checking is enabled. Using terminal names as correspondence points. Compiling Diva LVS rules... Net-list summary for /home/cher5606/LVS/layout/netlist count 33 nets 12 terminals 47 pmos 47 nmos Net-list summary for /home/cher5606/LVS/schematic/netlist count 33 nets 12 terminals 23 pmos 23 nmos

38. Logical_And LVS-2 Terminal correspondence points 1 !A 2 !Add 3 !B 4 !Cadd 5 !Cin 6 !Yadd 7 A 8 Add 9 B 10 Cin 11 gnd! 12 vdd!

39. Logical_And LVS-3 The net-lists match. layout schematic instances un-matched 0 0 rewired 0 0 size errors 0 0 pruned 0 0 active 94 46 total 94 46 nets un-matched 0 0 merged 0 0 pruned 0 0 active 33 33 total 33 33 terminals un-matched 0 0 matched but different type 0 0 total 12 12

40. Y_Output Schematic Wn = 10.35 um Wp = 26.55 um tPHL = .5 ns Inputs ADD, SUB, SL, LA, !Yadd, !Cin Outputs Y

41. Y_Output Layout

42. Carry Output Schematic Wn = 10.35 um Wp = 26.55 um t = 400 ps Inputs ADD, SUB, SL, !Cadd, !A Outputs Cout

43. Carry Output Layout

44. Carry Testbench

45. Carry Waveform

46. Output Testbench

47. Output Waveform

48. 1-Bit Schematic

49. 1 Bit ALU Layout

50. 1-Bit ALU Test Bench