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EE166 PROJECT Design Project 8 bit ALU

EE166 PROJECT Design Project 8 bit ALU. By Nisha Hemnani Yamini Venugopal Archana Karehalliraju. Agenda. Introduction D-FF Propogate & Generate Block Multiplexer Adder Circuit Conclusion. Functions Performed. Additon Xor And. 8 bit ALU Overview. Excel sheet. D FF Schematic.

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EE166 PROJECT Design Project 8 bit ALU

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  1. EE166 PROJECTDesign Project8 bit ALU By Nisha Hemnani Yamini Venugopal Archana Karehalliraju

  2. Agenda • Introduction • D-FF • Propogate & Generate Block • Multiplexer • Adder Circuit • Conclusion

  3. Functions Performed • Additon • Xor • And

  4. 8 bit ALU Overview

  5. Excel sheet

  6. D FF Schematic

  7. D FF Testbench

  8. Waveforms of D-ff

  9. Test bench

  10. DRC, LVS, of D-ff

  11. DRC, LVS, of D-ff

  12. DRC and Extracted View

  13. LVS

  14. Excel Sheet

  15. Propagate AOI 3333

  16. DRC and Extracted View

  17. Test bench

  18. MUX 3:1 AOI • Thoery about mux why we choose 3:1..becos we have to choose between S1, P1, G1.

  19. DRC and Extracted View

  20. Mux Layout

  21. Schematic

  22. Waveform of Adder circuit

  23. Schematic

  24. Black Cell Schematic

  25. XOR Schematic

  26. NC Verilog Simulation

  27. Adder Layout

  28. Cell LVS

  29. DRC Adder

  30. Extraction Report

  31. LVS Adder

  32. Specifications Timing = 2.67 ns Area = 206.9 x 700um2 Power = < 20mW

  33. Final Schematic

  34. Waveforms

  35. Final DRC

  36. Final Extraction Report

  37. Final Layout

  38. Acknowledgements • Thanks to Dr.Parent for valuable guidance.

  39. Work Distribution • D ff’s…….Nisha Hemnani • Final schematic…Nisha Hemnani • P and G AOI3333…Archana Karehalliraju • Mux…..Archana Karehalliraju • Adder….Yamini Venugopal

  40. Lessons Learned • Work with time oriented milestones. • Space for unplanned delays.

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